Patents Examined by Phung My Chung
  • Patent number: 7636875
    Abstract: A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: December 22, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert Floyd Payne
  • Patent number: 7363559
    Abstract: According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of the shifting of the first data. Next, it is determined whether the second data includes the token. In some aspects, a size of the IEEE 1149.1-compliant shift register is determined based on the second data.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventor: Jaemon D. Franko
  • Patent number: 7360130
    Abstract: An internal processing capability is added to a computer memory by adding a small processor, a small amount of processor RAM memory, a small amount of non-volatile memory, and some logic. During wafer testing the internal processor system allows the memory to be tested at full speed and substantially simultaneously with the testing of other memories on the wafer. At any stage after packaging, the part can be tested by having the host processor read the non-volatile memory, determine what test program to use, load it into the RAM memory, and run the Self-Test program. The internal processor system also allows additional functions such as data searching, data moving, and graphics primitives to be performed entirely within the memory.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: April 15, 2008
    Inventor: Jed Margolin
  • Patent number: 7356741
    Abstract: A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for performing tests, the BIST core including proven testing algorithms; a selectable tester interface for interfacing the BIST core with an external tester; and a selectable eDRAM interface for interfacing the BIST core with an eDRAM, the eDRAM including a plurality of memory cells for storing data. The present invention allows semiconductor device designers to keep to one testflow and reuse a proven BIST core over multiple ASIC (Application Specific Integrated Circuits) products/generations.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventor: Thomas Boehler
  • Patent number: 7353448
    Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: April 1, 2008
    Assignee: Marvell Semiconductor Israel Ltd.
    Inventor: Dror Barash
  • Patent number: 7331005
    Abstract: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: February 12, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ralf Arnold, Gerd Frankowsky, Wolfgang Spirkl
  • Patent number: 7328388
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: February 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 7322005
    Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding using non-Gray code maps for improved performance. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. In addition, the LDPC coded modulation symbol decoding can be employed to decode a signal that has been encoded using LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) encoding with non-Gray code mapping. By using the non-Gray code mapping, a performance improvement over such a system using only Gray code mapping may be achieved.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 22, 2008
    Assignee: Broadcom Corporation
    Inventors: Ba-Zhong Shen, Hau Thien Tran, Kelly Brian Cameron
  • Patent number: 7320102
    Abstract: A network processor [200] performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuits [308-308]. The network processor [200] includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: January 15, 2008
    Assignee: BBN Technologies Corp.
    Inventor: Walter C. Milliken
  • Patent number: 7299390
    Abstract: An interlinked chain of exclusive-or (XOR) logic gates and registers is formed by connecting a first input of each XOR logic gate to an output of a preceding register, and by connecting an input of each register to an output of a preceding XOR logic gate. Each XOR logic gate has a second input connected to receive an output from a respective data source. The interlinked chain further includes an originating XOR logic gate having its first input connected to an output of an originating data source rather than to a preceding register. The interlinked chain includes a terminating XOR logic gate having an output defined to provide an encrypted signature for the various data source outputs. Destructible bypass connections are provided to enable direct access to each data source in a secure environment and permanently disable direct access to each data source prior to release from the secure environment.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: November 20, 2007
    Assignee: Altera Corporation
    Inventor: Jayabrata Ghosh Dastidar
  • Patent number: 7296196
    Abstract: A nonvolatile memory device requires no additional dummy bytes between receipt of a read instruction and a scanning out of data from a first target memory location requiring incorporation of redundant memory bits. A set of most significant redundant memory bits corresponding to a range of regular memory locations may be read speculatively after a particular set of the highest order address bits are received. After a complete address is received, any requirement for substitution of redundant memory bits is known. If no substitution is required, the regular memory contents are read. Any requirement for a substitution of memory bits may require replacement of the entire location. A regular read operation continues after the first location is read. In this way, complete and correct data for the memory location are available after receipt of a read instruction with no additional delay for including any required redundant memory bits.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: November 13, 2007
    Assignee: Atmel Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7296197
    Abstract: Described herein are one or more implementations for facilitation of computer software testing. One or more implementations, described herein, determine logical type of one or more test input-parameters based upon metadata placed on a function under test (FUT) of software. Using that determined logical type, an implementation generates data values. In some instances, those generated values are values selected from a repository of data values with associated logical types. The selection is based upon the determined logical type. After generating data values for testing the FUT, an implementation supplies the generated data values as input to the FUT.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: November 13, 2007
    Assignee: Microsoft Corporation
    Inventors: Kaushik Pushpavanam, Ujjwal Sarin
  • Patent number: 7284168
    Abstract: System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: October 16, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Michael Hill, Todd Mellinger, David Thomas Newsome
  • Patent number: 7281184
    Abstract: A test-device for testing an electric circuit comprises a data stream generator for generating a first data stream to be fed to an electric circuit which generates a second data stream in response to the first data stream and a comparison-device for comparing two data streams. The test-device comprises further a self-test device configured to generate a third data stream used to test the comparison-device. The test-device is further configured to operate in a first operation mode and in a second operation mode. The comparison-device is configured to compare the first data stream with the second data stream during the first operation mode and is configured to compare the first data stream with the third data stream during the second operation mode.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: October 9, 2007
    Assignee: Infineon Technologies AG
    Inventor: Sven Boldt
  • Patent number: 7278078
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: October 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 7275197
    Abstract: A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes an operation order holding unit for holding information indicating that a test operation by a first testing module should be performed before a test operation by a second testing module, a trigger return signal receiving unit for receiving a trigger return signal from the first testing module, the trigger return signal indicating that the first testing module has completed the test operation thereof, when the test operation of the first testing module has been completed, and a trigger signal supplying unit for supplying a trigger signal to the second testing module, the trigger signal indicating that the second testing module should start the test operation thereof, when the trigger return signal receiving unit receives the trigger return signal.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: September 25, 2007
    Assignee: Advantest Corporation
    Inventors: Kenji Inaba, Masashi Miyazaki
  • Patent number: 7275198
    Abstract: Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: September 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hee Kim, Ho-Kyu Choi, Youn-Sun Kim, Hwan-Joon Kwon
  • Patent number: 7269767
    Abstract: The present invention has been made to obtain a magnetic disk apparatus and the like capable of using a patrol region in the magnetic disk to detect a location in need of maintenance in hardware equipment around the magnetic disk in a separate manner from the disk itself and thereby avoiding useless replacement and operating the magnetic disk apparatus at low cost. In a preventive maintenance detection for a magnetic disk apparatus having a patrol function that uses a patrol region in the magnetic disk to determine the presence/absence of the need of preventive maintenance, a data pattern for detecting crosstalk in hardware equipment around the disk is generated, a write command or read command corresponding to the generated data pattern is executed, and the crosstalk is determined/detected based on the command execution result.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 11, 2007
    Assignee: Fujitsu Limited
    Inventors: Norihide Kubota, Hideo Takahashi, Hiroaki Ochi, Yoshihito Konta, Yasutake Sato, Tsukasa Makino, Mikio Ito, Hidejirou Daikokuya, Kazuhiko Ikeuchi, Shinya Mochizuki
  • Patent number: 7266743
    Abstract: A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first distributed shift generator to send a shift-enable-flop signal to be received by the first group of scan chains. The processor including a second distributed shift generator associated with a second time domain, wherein the second distributed shift generator is coupled to a second group of scan chains, the second distributed shift generator to send a shift-enable-flop signal to be received by the second group of scan chains. The processor including a scan test controller coupled to the first and second distributed shift generators, the scan test controller to provide clocking signals for the first time domain and the second time domain for performing an at-speed test of circuits coupled to the first group of scan chains.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: September 4, 2007
    Assignee: Intel Corporation
    Inventors: Atul S. Athavale, Jason R. Ng
  • Patent number: 7263639
    Abstract: A combinatorial at-speed scan testing. A processor including a plurality of distributed slave counters. Each distributed slave counter coupled to a group of scan chains, each distributed slave counter to generate shift-enable-flop signals to be received by the group of scan chains coupled to each distributed slave counter, the shift-enable-flop signals based at least in part on an external shift-enable signal received by the processor. A scan test controller coupled to the plurality of distributed slave counters to provide control signals to the plurality of distributed slave counters to perform an at-speed test of the processor.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Atul S. Athavale, Jason R. Ng