Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: A system for testing a memory page of a computer while an operating system is active. The system includes a hook function and a pattern generator. The hook function has software instructions that takes the place of a memory allocation/release scheme of the operating system. The system stores a test pattern generated by the pattern generator in the memory page upon receiving a request to release the memory page. Upon receiving a request to allocate the memory page, the system verifies the test pattern is correct to ensure the memory page is not defective. If the test pattern is incorrect, the defective memory page is removed from service.

Abstract: A method for performing CRC calculations on packets with dynamic headers is disclosed. The header may be changed during transmission across a network. When the header is changed, a CRC associated with the header is recalculated such that a residue of the initial seed value is always obtained. A final CRC covers the entire packet including the header and its header CRC, or just the data portion of the packet. The final CRC remains valid and unchanged during transmission of the packet, allowing an endpoint along the network to confirm the validity of the entire packet. By only changing the CRC associated with the changed portion of the packet (the header CRC), the introduction of errors during transmission of the packet is minimized.

Abstract: The scan test circuit according to one embodiment of the present invention includes a noninversion/inversion control circuit inserted and connected between a sequential circuit and a combinational circuit included in a path to be subjected to a scan test, the noninversion/inversion control circuit not inverting or inverting scan data output from the sequential circuit, on outside of said sequential circuit at arbitrary timing.

Abstract: A flexible Boundary Scan test system is disclosed. The system includes an interpreter module operable to execute a program element selected from a plurality of program elements that include at least one instruction type having an interface to identify and execute selected functions wherein each of the selected functions has associated therewith at least one data information item. In one aspect of the invention, selected ones of the functions are composed of a plurality of functions. In another aspect of the invention, the instruction includes parameters and adornments for determining the selected function execution.

Abstract: A transmitter simultaneously performs channel coding and rate matching in a CDMA mobile communication system. The transmitter encoders input bits into coded bits at a given mother code rate, and performs puncturing on the coded bits in order to match the number of coded bits to a predetermined code rate. Thereafter, the transmitter simultaneously performs rate matching for repeating or puncturing the coded bits in order to match the number of coded bits to the number of bits transmitted over a radio channel.

Abstract: A decoding system and method for decoding parallel concatenated parity-check code defines a parity check matrix (e.g., a sparse parity check matrix) for the parallel concatenated parity check code. One or more bipartite graph representations are determined based on the parity check matrix with each of the one or more bipartite graph representations including bit nodes and check nodes. At least one of the one or more bipartite graph representations is decoded using an iterative decoding process (e.g., using an algorithm based on belief propagation).

Abstract: The invention provides a test device for testing circuit units (101a–101n) to be tested, having connecting units (106a–106n) for connecting the circuit units (101a–101n) to be tested to the test device, a test system (100) and an output unit (108) for outputting test result data, the test device having a determining unit (103) for determining those of the measurement data (110a–101n) which correspond for a predeterminable number of circuit units (101a–101n) to be tested, and for defining the corresponding measurement data (110a–110n) as the expected data (111); and comparison units (104a–104n) for comparing the measurement data (110a–110n) generated by the circuit units (101a–101n) to be tested in a manner dependent on the test data (112) written in with the expected data (111) in order to obtain comparison data (115a–115n).

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: A system maintains a copy of data stored in a first memory device in a redundant distinct second memory device. Upon detecting an uncorrectable error in the first memory device, the system then relies on the copy of the data in the second memory device. The system, once it starts relying on the data in the second memory device, may then test the first memory device to determine if the uncorrectable error was due to a physical problem or a transient event. If the first memory device is then found to be working correctly, it may, in turn, become a redundant memory device for the second memory device.

Abstract: One embodiment of a method may include partitioning data into segments of the data, storing in memory a set of checksums of the segments of the data, selecting a portion of the data, and determining a checksum of the portion of the data. The portion of the data may comprise a subset of the segments of the data and/or at least one part of at least one segment of the data. The checksum of the portion of the data may be determined, based, at least in part, upon a checksum of the subset of the segments and/or a checksum of the at least one part of the at least one segment. The checksum of the subset of the segments may be based, at least in part, upon respective checksums, read from the checksums stored in the memory, of segments of the data comprised in the subset of the segments.

Abstract: A semiconductor integrated circuit disclosed herein comprising: a phase control circuit which shifts a phase of a first clock signal based on a phase control signal and outputs a second clock signal; a first flip-flop to which one of the first clock signal and the second clock signal is inputted as a first operation clock signal, and which outputs evaluation data; a circuit under test which performs a predetermined process based on the evaluation data and outputs a result of the process as output data; and a second flip-flop to which the other of the first clock signal and the second clock signal is inputted as a second operation clock signal and the output data is inputted, and which outputs the output data inputted from the circuit under test.

Abstract: A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.

Abstract: A method for generating satellite clock corrections for a WADGPS network computers satellite clock corrections after removing other substantial error components. Errors caused by the ionosphere refraction effects are removed from GPS measurements taken at reference stations using dual-frequency GPS measurements. The multipath noise are removed by smoothing of GPS pseudorange code measurements with carrier-phase measurements. The tropospheric refraction effect can be largely removed by modeling, and if desired, can be improved by the use of small stochastic adjustments included in the computation of the clock correction. After removing the above error factors, satellite clock corrections are computed for individual reference stations, and an average clock correction is formed for each of a plurality of satellites by taking an average or weighted average of the satellite clock corrections over reference stations to which the satellite is visible.

Abstract: A method of turbo decoding using soft input-soft output information. A vector of data is sampled from a channel of data. The vector of data is then processed to output a final code word of bits. A final reliability vector of reliability values associated with the final code word is generated, such that each bit of the final code word of bits has a corresponding reliability value in the final reliability vector. Corresponding reliability values for one or more bit positions of the final code word are determined by a difference of distance metrics, and corresponding reliability values for one or more bit positions of the final code word are determined utilizing a numerical approximation.

Abstract: Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronou

Abstract: A testing method involves information being written to memory addresses and being read from the memory addresses. The method which logically combines parallel memory bank actuation of the memory addresses using an interleaved mode, which is implemented in relation to disjunct subareas of the memory banks, with one another. This shortens the test time required for testing the semiconductor memory.

Abstract: Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.

Abstract: A radiation hard logic device such as a divider is disclosed. The logic device includes a voter module to determine an error free logic device output, a feedback module to generate a correction signal and provide the signal to a logic correction module to correct the erroneous device output at substantially the same time that the erroneous logic device is presented to the logic correction module.

Abstract: Examiner's permission under MPEP §608.01(q) and 37 CFR §1.125(b) is requested to submit a substitute specification and abstract. The substitute specification corrects typographical errors, grammar and formatting. No new matter has been added. The substitute specification and abstract contain no new matter to the specification of record. A marked-up version is attached along with a clean version in an appendix attached hereto.