Patents Examined by Phuong Phu
  • Patent number: 11558533
    Abstract: A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: January 17, 2023
    Assignee: GENESYS LOGIC, INC.
    Inventor: Ching-Hsiang Lin
  • Patent number: 11556093
    Abstract: A method for calibrating a light smart watch includes: providing an FPC soft board under a dial, a size of the FPC soft board matching a size of the dial, the FPC soft board is divided into a plurality of partitions, each partition is insulated from other partitions, and each of watch hands and each partition form a capacitor in turn when the watch hands run; detecting a capacitance change amount of each partition, determining positions of partitions where the watch hands are currently located, and determining a current time indicated by the watch hands, according to the positions of partitions where the watch hands are currently located; comparing the current time indicated by the watch hands with a current time of a mobile terminal to determine a time error; and adjusting the watch hands, according to the time error to run in sync with the time of the mobile terminal.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 17, 2023
    Assignee: GOERTEK TECHNOLOGY CO., LTD.
    Inventor: Xun Liu
  • Patent number: 11552777
    Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: January 10, 2023
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Vincent Onde, Diarmuid Emslie, Patrick Valdenaire
  • Patent number: 11546127
    Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gaurav Malhotra, Amir Amirkhany, Jalil Kamali
  • Patent number: 11546128
    Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Jeon, Dae Sik Park, Jae Young Jang, Byung Cheol Kang, Seung Duk Cho
  • Patent number: 11531639
    Abstract: Techniques for denoising an electromagnetic signal are disclosed. The techniques utilize an antenna, a weight adaptation component, a reservoir computer including a computer interpretable neural network, a delay embedding component, and an output layer computer. The techniques include passively acquiring an electromagnetic signal by the antenna, producing a plurality of reservoir state values by the reservoir computer based on the electromagnetic signal, collecting the plurality of reservoir state values by the delay embedding component into a historical record, determining a plurality of reservoir state value weights by the weight adaptation component based at least in part of the historical record, scaling, by the plurality of reservoir state value weights, to produce a plurality of output values, the plurality of reservoir state values by the output layer computer, and outputting the plurality of output values, where the scaling occurs over a plurality of clock cycles of a clock for the system.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 20, 2022
    Assignee: THE BOEING COMPANY
    Inventors: Peter Petre, Shankar Rao, Gabriel Virbila
  • Patent number: 11509274
    Abstract: Techniques are provided for automatic gain control processing to reduce adverse effects associated with clipped samples resulting from conversion of analog signals to digital signals. A methodology according to an embodiment includes identifying a clipped sample of the digital signal, for example by comparison of the digitized sample values to a threshold value associated with a full scale value of the converter. The method also includes applying a window function to portions of the digital signal. The window function is configured to attenuate samples of the digital signal within a region centered on the identified clipped sample. A Hilbert finite impulse response (FIR) filter may be applied to the digital signal prior to applying the window function. Parameters of the window function are selected based on frequency response characteristics of the FIR filter and on signal to noise ratio requirements of an application that receives the windowed digital signal.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: November 22, 2022
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Michael H. Stockmaster, Ryan D. Downey
  • Patent number: 11502812
    Abstract: A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 15, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Vivek Sarda
  • Patent number: 11502814
    Abstract: Disclosed are a device and method for realizing data synchronization. The device may include a synchronization circuit for a plurality of radio frequency (RF) chips, configured to realize work clock synchronization among the plurality of RF chips; and/or, a synchronization circuit for a plurality of channels in a single chip, configured to realize data synchronization among the plurality of channels in the single chip.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 15, 2022
    Assignee: ZTE CORPORATION
    Inventor: Peng Li
  • Patent number: 11496198
    Abstract: The present disclosure describes methods, device, system that provide a codebook indication operation. In one example, a codebook indication method includes: receiving by a terminal device, a transmission parameter indication information indicating an index of one codebook subset configuration of three codebook subset configurations in the terminal device from a base station, wherein the three codebook subset configurations in the terminal device are related to fully coherent, partial coherent, and incoherent respectively, and the codebook subset configuration related to fully coherent includes M indexes, the codebook subset configuration related to partial coherent includes N indexes, and the codebook subset configuration related to incoherent includes K indexes, wherein M is an integer larger than N, and N is larger than K; and determining a transmission layer and precoding matrix associated with the index according to the transmission parameter indication information.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 8, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xianda Liu, Kunpeng Liu, Zukang Shen, Yan Cheng
  • Patent number: 11489656
    Abstract: A wireless station includes at least one oscillator to output a reference signal, and an error calculator to calculate a frequency of the reference signal and calculate a frequency error by subtracting a target frequency of the reference signal from the calculated frequency of the reference signal. The wireless station further includes a modulation data generator to generate modulation data by adding a correction value, varying in negative correlation with the frequency error calculated by the error calculator, to data to be transmitted, and a modulator to conduct frequency modulation on the basis of the modulation data and the reference signal.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: November 1, 2022
    Assignee: ICOM INCORPORATED
    Inventors: Takeo Tomita, Masaki Akasaka, Yasuo Ueno
  • Patent number: 11481217
    Abstract: A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 25, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Kyoungho Kim, Changsik Yoo, Baekjin Lim
  • Patent number: 11483059
    Abstract: A method of operating a TDD-based interference cancellation repeater, the method comprises setting a compensation gain of a gain compensator differently in an uplink communication period and a downlink communication period, setting an optimal coefficient of an adaptive filter in the uplink communication period and an optimal coefficient of the adaptive filter in the downlink communication period the same, based on the set compensation gain of the gain compensator and removing an interference signal in the uplink communication period or the downlink communication period according to the set optimal coefficient of the adaptive filter.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: October 25, 2022
    Assignees: SOLiD, INC., FOUNDATION OF SOONGSIL UNIVERSITY—INDUSTRY COOPERATION
    Inventors: Nagwon Kwon, Hyunchae Kim, Chonghoon Kim
  • Patent number: 11477004
    Abstract: A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 18, 2022
    Assignee: NVIDIA CORP.
    Inventors: Pervez Mirza Aziz, Vishnu Balan, Viswanath Annampedu
  • Patent number: 11469789
    Abstract: An electronic lock can enter a lockdown mode in response to a lockdown command comprising a mechanical command, e.g. a button or door handle being pressed on the lock in a predefined time-series sequence, or touching the lock in a time-series sequence). Alternatively, an audio or visual command can be issued, e.g. saying certain words or making a hand gesture. The lock may require additional authentication before executing the lockdown command, e.g. recognizing an authorized electronic key. Other embodiments are also provided.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 11, 2022
    Assignee: SecureALL Corporation
    Inventors: Arun Kumar Sharma, Michael Wurm, Richard Schaffzin, Prajakta Setty, Deep Kumar
  • Patent number: 11463233
    Abstract: Methods, apparatus, and systems for communication over a C-PHY interface are disclosed. A transmitting device has a driver circuit configured to drive a three-wire bus in accordance with a symbol received at an input of the driver circuit, a pattern detector receives a sequence of symbols to be transmitted over the three-wire bus in a plurality of transmission symbol intervals, and a selection circuit responsive to a select signal provided by the pattern detector and configured to select between delayed and undelayed versions of a current symbol to drive the input of the driver circuit during a corresponding transmission symbol interval. The select signal may select the delayed version of the current symbol when a combination of the current symbol with an immediately preceding symbol cause the pattern detector to indicate a pattern match.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 4, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Chulkyu Lee, George Alan Wiley
  • Patent number: 11463149
    Abstract: Embodiments of the present disclosure provide methods for transmitting an uplink signal and a downlink signal. A method for transmitting an uplink signal comprises detecting whether there is a beam failure; if there is a beam failure, determining at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information; and transmitting a beam failure recovery request message to a base station, the beam failure recovery request message being used for informing the base station of at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information. A method for transmitting a downlink signal comprises detecting a beam failure recovery request message, determining at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information in the UE; and transmitting a feedback message corresponding to the beam failure recovery request message.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Qi Xiong, Chen Qian, Bin Yu
  • Patent number: 11451367
    Abstract: A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: September 20, 2022
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, James St. Leger Harley, Tung Trong Nguyen
  • Patent number: 11451419
    Abstract: The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Non-linear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: September 20, 2022
    Assignee: The Research Foundation for The State University
    Inventors: Xiaohua Li, Robert Thompson
  • Patent number: 11444746
    Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: September 13, 2022
    Assignee: Analog Devices, Inc.
    Inventors: John Kenney, Robert Schell