Patents Examined by Phuong Phu
  • Patent number: 11916625
    Abstract: An antenna arrangement comprises a body which in turn comprises a plurality of antenna devices, the antenna arrangement being characterized in that the body has a flexible structure and an elongated shape.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Pål Frenger, Jan Hederen, Martin Hessler, Giovanni Interdonato
  • Patent number: 11909492
    Abstract: A transmission method for transmitting a first modulated signal and a second modulated signal in the same frequency at the same time. Each signal has been modulated according to a different modulation sheme. The transmission method applies precoding on both signals using a fixed precoding matrix, applies different power change to each signal, and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: February 20, 2024
    Assignee: SUN PATENT TRUST
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 11909485
    Abstract: The present disclosure describes methods, device, system that provide a codebook indication operation. In one example, a codebook indication method includes: receiving by a terminal device, a transmission parameter indication information indicating an index of one codebook subset configuration of three codebook subset configurations in the terminal device from a base station, wherein the three codebook subset configurations in the terminal device are related to fully coherent, partial coherent, and incoherent respectively, and the codebook subset configuration related to fully coherent includes M indexes, the codebook subset configuration related to partial coherent includes N indexes, and the codebook subset configuration related to incoherent includes K indexes, wherein M is an integer larger than N, and N is larger than K; and determining a transmission layer and precoding matrix associated with the index according to the transmission parameter indication information.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xianda Liu, Kunpeng Liu, Zukang Shen, Yan Cheng
  • Patent number: 11902000
    Abstract: Embodiments of the present disclosure provide methods for transmitting an uplink signal and a downlink signal. A method for transmitting an uplink signal comprises detecting whether there is a beam failure; if there is a beam failure, determining at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information; and transmitting a beam failure recovery request message to a base station, the beam failure recovery request message being used for informing the base station of at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information. A method for transmitting a downlink signal comprises detecting a beam failure recovery request message, determining at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information in the UE; and transmitting a feedback message corresponding to the beam failure recovery request message.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 13, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Qi Xiong, Chen Qian, Bin Yu
  • Patent number: 11902408
    Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: February 13, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gaurav Malhotra, Amir Amirkhany, Jalil Kamali
  • Patent number: 11870501
    Abstract: The present invention relates to a method for communicating data acoustically. The method includes segmenting the data into a sequence of symbols; encoding each symbol of the sequence into a plurality of tones; and acoustically generating the plurality of tones simultaneously for each symbol in sequence. Each of the plurality of tones for each symbol in the sequence may be at a different frequency.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 9, 2024
    Assignee: Sonos Experience Limited
    Inventors: Daniel John Jones, James Andrew Nesfield
  • Patent number: 11855813
    Abstract: The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Nonlinear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: December 26, 2023
    Assignee: The Research Foundation for SUNY
    Inventors: Xiaohua Li, Robert Thompson
  • Patent number: 11856080
    Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 26, 2023
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Vincent Pascal Onde, Diarmuid Emslie, Patrick Valdenaire
  • Patent number: 11856082
    Abstract: Apparatuses and methods of widespread equispatiated phase generation of a clock divided by a non-integer factor are described. One integrated circuit includes a clock divider and a phase generator. The clock divider receives a single-phase clock signal from a clock source and generates a divided clock signal. The phase generator receives the divided clock signal and the single-phase clock signal and generates multiple phase signals using the divided clock signal and the single-phase clock signal. The phase signals are equispatiated.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: December 26, 2023
    Assignee: Infineon Technologies AG
    Inventor: Andrea Bandiziol
  • Patent number: 11855648
    Abstract: A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Gaurav Malhotra
  • Patent number: 11855800
    Abstract: Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: December 26, 2023
    Assignee: Renesas Electronics America Inc.
    Inventors: Leonid Goldin, Greg Anton Armstrong
  • Patent number: 11849018
    Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: December 19, 2023
    Assignee: NXP B.V.
    Inventors: Olivier Jérôme Célestin Jamin, Olivier Susplugas, Olivier Frédéric Guttin
  • Patent number: 11848727
    Abstract: A plurality of transmit antennas of a radio transmission device and a plurality of receive antennas of a radio reception device are located under the sea that is a line-of-sight environment, wherein the radio transmission device selects a frequency channel to be used based on an index value per frequency channel indicating orthogonality between the transmit and receive antennas defined based on a distance between the transmit and receive antennas and an angle indicating a direction of arrival of a radio signal, an interval between the plurality of transmit antennas, an interval between the plurality of receive antennas, and a modulation scheme, the distance between the transmit and receive antennas and the angle indicating the direction of arrival of the radio signal estimated by the radio reception device, and a desired bit error rate to be predetermined, selects the modulation scheme for providing a maximum transmission capacity per the selected frequency channel, separates transmission data into a pluralit
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 19, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Marina Nakano, Yosuke Fujino, Hiroyuki Fukumoto, Kazunori Akabane
  • Patent number: 11838152
    Abstract: A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the thi
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: December 5, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Takashi Toi
  • Patent number: 11838090
    Abstract: Various embodiments of the present disclosure provide a method for information sharing. The method which may be performed by a first network node comprises receiving a first measurement report from a terminal device. The terminal device may be capable of communicating with the first network node over a first connection. The method further comprises transmitting first measurement information based at least in part on the first measurement report to a second network node. The terminal device may be capable of communicating with the second network node over a second connection.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 5, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Chunhui Liu, Huaisong Zhu
  • Patent number: 11831323
    Abstract: A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 28, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Marcus Van Ierssel, Prabhnoor Singh Kainth, Nanyan Wang
  • Patent number: 11824966
    Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.
    Type: Grant
    Filed: January 31, 2021
    Date of Patent: November 21, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Yong-Ren Fang, Yu-Hsiang Wang, Che-Wei Yeh
  • Patent number: 11811905
    Abstract: A system and method compensate for latency, where the system includes a transmit module and a receive module that implements a DLL in a pseudo synchronous communications link. The method includes determining maximum data latency based on synchronous latencies and analog delays; measuring an actual data path latency by determining a delay in receiving a test pattern transmitted from the transmit module at the receive module using a common synchronization pulse provided the transmit and receive modules simultaneously or with a known fixed latency separation during calibration; determining a latency difference between the determined maximum data latency and the measured data path latency; and compensating for the latency difference for a subsequent data signal transmitted from the transmit module in the pseudo synchronous communications link, such that a total latency of the system with regard to the subsequent data signal is equal to the maximum data latency for the system.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: November 7, 2023
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventor: Donald M. Logelin
  • Patent number: 11804947
    Abstract: A radio apparatus correlates signal data with stored synchronization data to determine correlation data. The signal data represents a received radio-frequency signal that encodes a data frame, which has a synchronization preamble with a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The radio apparatus identifies a set of peaks in the correlation data, and uses a timing criterion to identify a plurality of subsets of the set of peaks, such that time values of the peaks of each identified subset satisfy the timing criterion. The radio apparatus calculates a correlation score Cj for each of the identified subsets from correlation values of the subset's peaks, and uses the correlation scores Cj to select a subset from the plurality of subsets. Timing or frequency synchronization information for the radio apparatus is determined from the peaks of the selected subset.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: October 31, 2023
    Assignee: Nordic Semiconductor ASA
    Inventor: Sverre Wichlund
  • Patent number: 11804945
    Abstract: A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juyun Lee, Vishnu Kalyanamahadevi Gopalan Jawarlal, Kang Jik Kim, Hyo Gyuem Rhew, Jae Hyun Park