Abstract: A method for calibrating a receiver of an isolator product includes adjusting a peaking frequency of a receiver signal path of a first integrated circuit die of the isolator product and a gain of the receiver signal path based on a predetermined peaking frequency, a predetermined gain, a first level of a diagnostic signal during a first interval, and a second level of the diagnostic signal during a second interval. The first interval and the second interval are non-overlapping intervals. The method may include receiving a calibration signal on a differential pair of nodes of the receiver signal path of the first integrated circuit die. The method may include generating a diagnostic signal corresponding to an average amplitude of a received version of the calibration signal.

Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Abstract: The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Abstract: Communication devices and systems with correct regeneration of an audio signal are disclosed. In one example, a communication device measures a number of predetermined reference clocks included in one cycle of a frequency divided signal, on the basis of an audio master clock having a frequency obtained by multiplying a frequency of a sampling clock to sample an audio signal, a frequency division ratio of a frequency divided signal of the audio master clock, and a predetermined reference clock. A packet generator generates a packet including information including the measured number, a bit width of serial data (SD) conforming to an Inter-IC Sound (I2S) standard, the frequency of the sampling clock, a frequency division ratio of the frequency divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

Abstract: Provided are a phase detection method and apparatus for a clock signal, and a communication device. A clock signal of a clock to be detected is sampled according to sampling periods set by a sampling clock; a phase angle value corresponding to a sampled clock signal in a current sampling period is obtained according to a mapping relationship between sampled signals and phase angle values; a phase difference corresponding to the current sampling period is subtracted from the phase angle value to obtain an initial phase value of the clock to be detected in the current sampling period, wherein the phase difference is a phase difference between the clock to be detected and the sampling clock in the current sampling period; and after the sampling ends, a final phase value of the clock to be detected is obtained according to initial phase values obtained in respective sampling periods.

Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

Abstract: An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. The processing mode selection may include a single processing mode, a multi-processing mode, or a full processing mode. The processing mode selection may be associated with an aspect of a wireless protocol. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

Abstract: A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

Abstract: The disclosure provides a method and a device for multi-antenna transmission in a base station and a User Equipment (UE). The UE, in turn, receives a first higher-layer signaling, monitors a first-type physical layer signaling in a first radio resource pool, and receives second downlink information in a second radio resource pool. The first higher-layer signaling is used for determining first information and second information, and the first information is used for multi-antenna related receiving in the first radio resource pool. The first-type physical layer signaling is detected, and the first-type physical layer signaling is used for multi-antenna related receiving in the second radio resource pool, or, the first-type physical layer signaling is not detected, and the second information is used for multi-antenna related receiving in the second radio resource pool. The second radio resource pool is related to the first radio resource pool.

Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus of a terminal in a wireless communication system is provided. The apparatus includes at least one transceiver and at least one processor operatively coupled to the at least one transceiver. The at least one processor is configured to control the transceiver to communicate through a cell determined based on information regarding a strength of a received signal for a first cell and a path diversity (PD) for the first cell. The PD comprises information regarding paths associated with the first cell.

Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

Abstract: A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

Abstract: A device configured to perform wireless communication includes: a pre-distortion circuit configured to generate a pre-distorted input signal by performing pre-distortion on an input signal based on a parameter set comprising a plurality of coefficients; a power amplifier configured to generate an output signal by amplifying an RF signal based on the pre-distorted input signal; and a parameter obtaining circuit configured to obtain second memory polynomial modeling information corresponding to an operating frequency band based on first memory polynomial modeling information corresponding to each of a plurality of frequency sections and obtain a parameter set according to an indirect learning structure by using the second memory polynomial modeling information.

Abstract: A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.