Patents Examined by Phuong Phu
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Patent number: 11245461Abstract: A transmission method for transmitting a first modulated signal and a second modulated signal in the same frequency at the same time. Each signal has been modulated according to a different modulation scheme. The transmission method applies precoding on both signals using a fixed precoding matrix, applies different power change to each signal, and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.Type: GrantFiled: November 25, 2020Date of Patent: February 8, 2022Assignee: SUN PATENT TRUSTInventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
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Patent number: 11239992Abstract: A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.Type: GrantFiled: March 24, 2021Date of Patent: February 1, 2022Assignee: Samsung Display Co., Ltd.Inventors: Michael Wang, Kyunglok Kim
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Patent number: 11239018Abstract: The present invention is directed to electrical circuits. and more specially, inductor designs that reduce on-chip electromagnetic coupling in certain applications. In a specific embodiment, the present invention provides an inductor that includes coils that are configured to generate magnetic fields of opposite polarities. The electromagnetic fields generated by the inductor coils substantially cancel out with each other, thereby minimizing parasitic inductance of the inductor and reducing interference with operations of other components in an integrated circuit. There are other embodiments as well.Type: GrantFiled: November 12, 2020Date of Patent: February 1, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: Marco Garampazzi, Matteo Pisati
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Patent number: 11239872Abstract: A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.Type: GrantFiled: October 29, 2020Date of Patent: February 1, 2022Assignee: SK hynix Inc.Inventors: Joo-Hyung Chae, Dae Han Kwon
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Patent number: 11233518Abstract: A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.Type: GrantFiled: September 9, 2020Date of Patent: January 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Geumyoung Tak
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Patent number: 11217755Abstract: Methods, systems, and apparatus for monitoring and controlling electronic devices using wired and wireless protocols are disclosed. The systems and apparatus may monitor their environment for signals from electronic devices. The systems and apparatus may take and disambiguate the signals that are received from the devices in their environment to identify the devices and associate control signals with the devices. The systems and apparatus may use communication means to send control signals to the identified electronic devices. Multiple apparatuses or systems may be connected together into networks, including mesh networks, to make for a more robust architecture.Type: GrantFiled: October 5, 2020Date of Patent: January 4, 2022Assignee: Crius Technology Group, LLCInventor: Phillip Bogdanovich
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Patent number: 11211196Abstract: Techniques are disclosed implementing a tunable transformer with additional taps in at least one of the three coils. The tunable transformer enables the resonant frequency within RF transceiver matching networks to be adjusted without substantially impacting the output power at resonance. The tunability of the transformer is partially driven by the insertion of additional coils within the transformer, which are selectively switched and may be further coupled with a tunable capacitance. The tunability of the transformer is further driven via the use of at least one multi-tap transformer coil, which allows electronic components to be coupled to different coil taps to thereby facilitate an adjustable DC inductance. Doing so counteracts changes in mutual inductance between the non-switched coils, and facilitates the stabilization of output power with shifts in resonant frequency.Type: GrantFiled: March 29, 2019Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Robin Drabinski, Andreas Loza, Vojkan Vidojkovic
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Patent number: 11212068Abstract: A node can include a clock; and mapper circuitry configured to determine a timestamp from the clock, and transmit the timestamp to a second node in a Radio over Ethernet (RoE) frame with the timestamp in a control subtype and with an operational code (opcode) that designates the timestamp is in the frame. The node can also include a demapper circuit configured to receive a second timestamp from the second node in a second RoE frame, and provide the second timestamp to a Differential Clock Recovery (DCR) circuit for adjustment of the clock to a second clock at the second node.Type: GrantFiled: August 24, 2020Date of Patent: December 28, 2021Assignee: Ciena CorporationInventors: Xiaojin Liu, Vahid Naraghi, Bashar Abdullah
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Patent number: 11211910Abstract: A device including one or more processors configured to, based on at least one of an external criterion or a signal-based criterion, output a first gain adjusted signal from a first gain adjuster or a second gain adjusted signal from a second gain adjuster as an input to an audio processing operation. The first gain adjusted signal corresponds to a first gain applied to an audio signal from a microphone and the second gain adjusted signal corresponding to a second gain applied to an audio signal from a microphone. The signal-based criterion is based on whether a first signal metric associated with the first gain adjusted signal or a second signal metric associated with the second gain adjusted signal is closer to a target metric.Type: GrantFiled: October 5, 2020Date of Patent: December 28, 2021Assignee: Qualcomm IncorproatedInventors: Jingbin Wang, Xiaoming Bao, Yu Chen
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Patent number: 11212017Abstract: An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.Type: GrantFiled: September 9, 2020Date of Patent: December 28, 2021Assignee: QUALCOMM IncorporatedInventors: Philip Jones, Georgios Mylonas, Andrew Gordon Summers, Oleg Popov
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Patent number: 11206167Abstract: A method of performing carrier frequency offset (CFO) estimation and/or time offset (TO) estimation at a radio equipment in a mobile communications system. The method allows, for each of a plurality of synchronization signal (SS) blocks (SSBs) in a SS Burst detected at said radio equipment, determining a CFO estimation and/or a TO estimation based on network information signal prediction. The method includes selecting at least some of said detected SSBs in said SSB Burst and combining the CFO estimations and/or the TO estimations to obtain improved CFO compensation and/or TO compensation for signal processing at said radio equipment.Type: GrantFiled: June 8, 2020Date of Patent: December 21, 2021Assignee: Hong Kong Applied Science and Technology Research Institute Company LimtedInventors: Haiming Zhang, Eddy Chiu, Man-Wai Kwan, Ho Yin Chan, Chunhua Sun, Kong Chau Tsang
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Patent number: 11201705Abstract: A data modulation method includes dividing, by a terminal device, to-be-sent data into N bit groups, wherein N?2 and N is an integer. The method also includes generating, by the terminal device, N complex symbol groups. An ith complex symbol group is obtained by processing an ith bit group based on a mapping rule corresponding to the ith bit group. The mapping rule corresponding to the ith bit group is determined based on at least a group identity of the ith bit group and a first parameter. The first parameter includes at least one of a pilot parameter, a hopping identity, a terminal device identity, a layer index of a non-orthogonal layer, or a hopping offset. The N bit groups correspond to at least two different mapping rules, 0?i?N?1, and i is an integer. The method further includes sending, by the terminal device, the N complex symbol groups.Type: GrantFiled: August 11, 2020Date of Patent: December 14, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Lei Wang, Lei Zhang, Yiqun Wu, Yan Chen
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Patent number: 11201723Abstract: Described herein are apparatus and methods for highly linear phase rotators with continuous rotation. A method includes generating a first code and a second code based on a desired offset to match a first and second frequency, respectively, calibrating the first code and the second code based on first phase rotator characteristics and second phase rotator characteristics, respectively, generating first N phase offset codes and second N phase offset codes from a calibrated first and second code, respectively, wherein each phase offset code constrains functionality of the first phase rotator and the second phase rotator, respectively, associated with a phase of the input clock to a defined region of operation, rotating a clock using the first N phase offset codes and the second N phase offset codes to match the first and second frequency, respectively.Type: GrantFiled: September 8, 2020Date of Patent: December 14, 2021Assignee: Ciena CorporationInventors: Jerry Yee-Tung Lam, Sadok Aouini, Naim Ben-Hamida
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Patent number: 11201722Abstract: A clock and data recovery circuit includes a first sampling phase detector and filter circuitry, a frequency detector circuit, a current source circuit, a band controller circuit, and a voltage controlled oscillator. The first sampling phase detector and filter circuitry generates a first voltage according to a pair of data and a first set of clock signals. The frequency detector circuit generates an up control signal and a down control signal according to the pair of data and the first set of clock signals. The current source circuit generates the first voltage according to the up control signal and the down control signal. The band controller circuit generates a band control signal according to the first voltage. The voltage controlled oscillator adjusts the first set of clock signals according to the band control signal and the first voltage.Type: GrantFiled: December 9, 2020Date of Patent: December 14, 2021Assignee: DigWise Technology Corporation, LTDInventors: Shih-Hao Chen, Chiou-Bang Chen, Wen-Pin Hsieh, Tai-Cheng Lee, Heng-Jui Liu
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Patent number: 11196425Abstract: An eye width monitor (EWM) for a clock and data recovery (CDR) circuit includes a delay circuit, a first multiplexer (MUX) and a calibration circuit. The delay circuit includes an input terminal and an output terminal. The first MUX, coupled to the delay circuit, includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first MUX is coupled to a clock input terminal of the EWM. The second input terminal of the first MUX is coupled to the output terminal of the delay circuit. The output terminal of the first MUX is coupled to the input terminal of the delay circuit. The calibration circuit, coupled to the delay circuit, is configured to receive an oscillation clock from the delay circuit and receive a reference clock, and calibrate the oscillation clock with the reference clock.Type: GrantFiled: August 18, 2020Date of Patent: December 7, 2021Assignee: NOVATEK Microelectronics Corp.Inventors: Che-Yi Lin, Yung-Cheng Lin
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Patent number: 11184202Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.Type: GrantFiled: May 18, 2020Date of Patent: November 23, 2021Assignee: Cable Television Laboratories, Inc.Inventor: Thomas H. Williams
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Patent number: 11184075Abstract: The present disclosure relates to a communication technique for combining a 5G communication system with IoT technology to support a higher data transmission rate than a 4G system, and a system thereof. The present disclosure can be applied to 5G communication and IoT related technology-based intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail business, security and safety related services, etc.). In addition, the present disclosure relates to a method and an apparatus for setting a reference signal in a 5G or NR system.Type: GrantFiled: December 28, 2018Date of Patent: November 23, 2021Inventors: Hoondong Noh, Youngwoo Kwak, Cheolkyu Shin
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Patent number: 11184208Abstract: A communication method, including: receiving a reference signal, where the reference signal is used for channel measurement; sending CSI, where the CSI is used to indicate one or more measured values, and the measured values are used to determine a precoding matrix, or the measured values are a precoding matrix. The measured value is related to a first group of base vectors and a second group of base vectors, or the measured value is related to a Kronecker product of the first group of base vectors and the second group of base vectors; the first group of base vectors includes an inverse discrete Fourier transform OFT vector or a Kronecker product of two IDFT vectors, and the second group of base vectors include a discrete Fourier transform DFT vector.Type: GrantFiled: August 12, 2020Date of Patent: November 23, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Haibao Ren, Huiying Zhu, Yuanjie Li
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Patent number: 11184057Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus of a terminal in a wireless communication system is provided. The apparatus includes at least one transceiver and at least one processor operatively coupled to the at least one transceiver. The at least one processor is configured to control the transceiver to communicate through a cell determined based on information regarding a strength of a received signal for a first cell and a path diversity (PD) for the first cell. The PD comprises information regarding paths associated with the first cell.Type: GrantFiled: September 6, 2017Date of Patent: November 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Doyoung Jung, Sangkyou Ryou, Junhee Jeong, Ingil Baek
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Patent number: 11177812Abstract: When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.Type: GrantFiled: November 24, 2020Date of Patent: November 16, 2021Assignee: GRACE CONNECTION MICROELECTRONICS LIMITEDInventors: Pei Wei Chen, Fang-Ren Liao, Po Huang Huang