Abstract: A method for synchronizing networks is disclosed. A first wired communication system having a first time base is set up in a first network. A second wired communication system having a second time base is set up in a second network. The first network and the second network are connected to a wireless communication system via a first translation unit and a second translation unit, respectively. The first translation unit and the second translation unit are synchronized to one another according to a third time base of the wireless communication system independently of the first time base and the second time base. A third synchronization message is transmitted from the first translation unit to the second translation unit. A transmission time for the third synchronization message in the third time base is determined and is used to synchronize the second time base to the first time base.

Abstract: Quadrature error correction (QEC) for radio transceivers are provided herein. In certain embodiments, a transceiver includes an in-phase (I) signal path including a first controllable amplifier coupled to a first data converter, and a quadrature-phase (Q) signal path including a second controllable amplifier coupled to a second data converter. The transceiver further includes a QEC circuit operable to correct for a quadrature error between the I signal path and the Q signal path by adjusting a gain of the first controllable amplifier and/or a gain of the second controllable amplifier.

Abstract: In a radio frequency module, the first inductor is disposed on the first principal surface of the mounting board and located on the first reception path through which a first reception signal of a first frequency passes, on an input side of the first low noise amplifier. The second inductor is disposed on the first principal surface of the mounting board and located on the second reception path through which a second reception signal of a second frequency lower than the first frequency passes, on an input side of the second low noise amplifier. The radio frequency component is disposed between the first inductor and the second inductor. A distance between the first inductor and the shielding layer is greater than a distance between the second inductor and the shielding layer. The first inductor overlaps the first low noise amplifier in a thickness direction of the mounting board.

Abstract: A phase calibration method includes: segmenting a received measurement sequence according to a preset rule; respectively determining a phase calibration factor of each of segmented measurement sequences, wherein the each of the segmented measurement sequences respectively corresponds to a segmented phase; and when performing a phase calibration on a sequence to be verified, according to a matching relation between a phase of the sequence to be verified and the each of the segmented phases, using the phase calibration factor corresponding to a matched segmented phase to perform the phase calibration on the sequence to be verified. The embodiments of the phase calibration method and the device are equivalent to dividing a non-linear measurement sequence into several approximately linear measurement sequences, and then calibrating each of the several approximately linear measurement sequences using a corresponding phase calibration factor respectively.

Abstract: In some embodiments, a digital clock management system includes input signal conversion circuitry, logic circuitry and output signal conversion circuitry. The input signal conversion circuitry converts input signals to corresponding first digital data streams, each of which contains digital data synchronized to a first data clock. First digital logic circuitry converts the first digital data streams to second digital data streams, each of which contains digital data synchronized to the first data clock, and converts the second digital data streams to third digital data streams, each of which contains digital data synchronized to a common clock. Second digital logic circuitry converts the third digital data streams to a single digital data stream. The output signal conversion circuitry converts the single digital data stream to a modulated output signal.

Abstract: In a transmitter apparatus, a known reference signal is superimposed on top of a data signal that is typically not known a priori to a receiver and the combined signal is transmitted. At a receiver, an iterative channel estimation and equalization technique is used to recover the reference signal and the unknown data signal. In the initial iteration, the known reference signal is recovered by treating the data signal as noise. Subsequent iterations are used to improve estimation of received reference signal and the unknown data signal.

Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

Abstract: An antenna arrangement comprises a body which in turn comprises a plurality of antenna devices, the antenna arrangement being characterized in that the body has a flexible structure and an elongated shape.

Abstract: A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.

Abstract: Systems and methods for a non-data-aided (NDA) approach to advanced OFDM timing are provided. This approach allows for accurate OFDM symbol timing and synchronization by avoiding inter-symbol interference (ISI) in multipath environments where an earliest arriving signal may not be the strongest signal. The NDA approach may rely on generating and applying a bias correction to a combined correlation result of the multi-path signals.

Abstract: A method, a computer-readable medium, and an apparatus are provided that enable use of a full transmission power for a UE having a first set of coherent antenna ports that is non-coherent to a second set of coherent antenna ports. The apparatus determines a transmission power for a physical uplink shared channel (PUSCH) transmission from at least one antenna port including splitting the transmission power among multiple antenna ports having non-zero power without scaling the transmission power, and wherein the UE includes at least a first antenna port that is non-coherent to a second antenna port. Then, the apparatus transmits the PUSCH transmission using the determined transmission power.

Abstract: Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

Abstract: A front-end module of a wireless device can replace a passive duplexer with an active duplexer that uses metamaterial matching circuits. The active duplexer can be formed from a power amplifier circuit and a low noise amplifier circuit that each include a metamaterial matching circuit. The combination of a power amplifier circuit and a low noise amplifier circuit that each utilize metamaterials to form the associated matching circuit can provide the functionality of a duplexer without including the additional circuitry of a stand-alone or passive duplexer. Thus, in certain cases, the front-end module can provide duplexer functionality without including a separate duplexer. Advantageously, in certain cases, the size of the front-end module can be reduced by eliminating the passive duplexer. Further, the loss introduced into the signal path by the passive duplexer is eliminated improving the performance of the communication system that includes the active duplexer.

Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Abstract: Methods, systems, and apparatus for monitoring and controlling electronic devices using wired and wireless protocols are disclosed. The systems and apparatus may monitor their environment for signals from electronic devices. The systems and apparatus may take and disambiguate the signals that are received from the devices in their environment to identify the devices and associate control signals with the devices. The systems and apparatus may use communication means to send control signals to the identified electronic devices. Multiple apparatuses or systems may be connected together into networks, including mesh networks, to make for a more robust architecture.

Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

Abstract: A time synchronization system includes a master and slave devices connected to each other via a data bus and a signal line dedicated to transmission of a fixed-period signal. The master device transmits the fixed-period signal through the signal line regularly at a transmission period, and transmits start time information indicating a transmission start time at which transmission of the fixed-period signal is started and transmission period information indicating the transmission period for the fixed-period signal through the data bus. The slave device counts a number of times the fixed-period signal is received and calculates, as a current time in the master device, a transmission time at which the master device transmits the fixed-period signal based on the number of times the fixed-period signal is received. The slave device corrects the time to the calculated current time in the master device.

Abstract: A clock data recovery unit includes: a phase corrector generating a first compensation clock signal and a second compensation clock signal based on an external clock signal; and a transition detector, wherein the transition detector comprises: a first integrator configured to integrate a first training pattern signal according to the first compensation clock signal to provide a first integration signal; and a second integrator configured to integrate the first training pattern signal according to the second compensation clock signal to provide a second integration signal, wherein, in response to the first integration signal being greater than a first reference voltage and the second integration signal being less than the first reference voltage, occurrence of a transition of the first training pattern signal is detected.

Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.

Abstract: A device configured to perform wireless communication includes: a pre-distortion circuit configured to generate a pre-distorted input signal by performing pre-distortion on an input signal based on a parameter set comprising a plurality of coefficients; a power amplifier configured to generate an output signal by amplifying an RF signal based on the pre-distorted input signal; and a parameter obtaining circuit configured to obtain second memory polynomial modeling information corresponding to an operating frequency band based on first memory polynomial modeling information corresponding to each of a plurality of frequency sections and obtain a parameter set according to an indirect learning structure by using the second memory polynomial modeling information.