Abstract: The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Non-linear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.

Abstract: A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.

Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.

Abstract: A phase locked loop (PLL) comprises: a reference oscillator to generate a reference clock having a reference frequency; a voltage controlled oscillator (VCO) to generate a VCO clock having a VCO frequency controlled in response to a control signal applied to the VCO; a first integrator to integrate the reference frequency into a first ramp slope; a second integrator to integrate the VCO frequency into a second ramp slope; and a slope comparator to generate a slope difference between the first ramp slope and the second ramp slope and that is conveyed by the control signal, such that the control signal is configured to drive the VCO frequency toward the reference frequency to minimize the slope difference and frequency lock the VCO frequency to the reference frequency.

Abstract: A range-finding and/or object-positioning system comprises one or more target devices; one or more reference devices communicating with said one or more target devices via one or more wireless signal sets, each wireless signal set comprising at least a first-speed signal having a first transmission speed and a second-speed signal having a second transmission speed, and the first transmission speed being higher than the second transmission speed; and at least one processing unit performing actions for determining at least one distance between one target device and one reference device based on the time difference between the receiving time of the first-speed signal and the receiving time of the second-speed signal of the wireless signal set communicated between said reference and target devices.

Abstract: An objective of the present technology is to provide a transmission device, a reception device, and a transceiver system of which miniaturization can be achieved. The transmission device includes an oscillator configured to oscillate a first clock signal; and a register signal reception unit configured to receive a register signal transmitted from a reception device and used for controlling the first clock signal. The reception device includes a signal generation unit configured to generate a register signal for controlling a first clock signal transmitted from the transmission device based on a comparison result obtained by comparing a reference clock signal with one of the first clock signal and a second clock signal which is based on the first clock signal; and a register signal transmission unit configured to transmit the register signal generated by the signal generation unit to the transmission device.

Abstract: A system for time synchronization of a network element including a GNSS receiver operative to receive at least one signal from at least one but less than four GNSS satellites, a locator operative to supply a location of a network element including the GNSS receiver to the GNSS receiver and a time synchronization calculator operative to time synchronize the network element with the GNSS satellites based on the at least one signal and the location.

Abstract: Embodiments of the present disclosure provide methods for transmitting an uplink signal and a downlink signal. A method for transmitting an uplink signal comprises detecting whether there is a beam failure; if there is a beam failure, determining at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information; and transmitting a beam failure recovery request message to a base station, the beam failure recovery request message being used for informing the base station of at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information. A method for transmitting a downlink signal comprises detecting a beam failure recovery request message, determining at least one of whether there is a candidate downlink transmission beam(s) or candidate downlink transmission beam information in the UE; and transmitting a feedback message corresponding to the beam failure recovery request message.

Abstract: System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.

Abstract: A reference-less dock and data recovery device includes a CDR circuit, an oscillator circuit, and a processor. The CDR circuit is configured to generate a first clock signal through synchronization according to a data signal having a first frequency in a first time period. The oscillator circuit is configured to output an oscillating clock signal according to the first clock signal, A frequency of the oscillating clock signal is substantially identical to that of the first clock signal. The processor oversamples the data signal having a second frequency in a second time period to generate a simulated preparation signal conforming to the second frequency. The CDR circuit is configured to generate a second clock signal through synchronization according to the simulated preparation signal. Before generating the second clock signal, the CDR circuit is synchronized to the oscillating clock signal to maintain outputting of the first clock signal.

Abstract: An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

Abstract: A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a power amplifier disposed on the module board; a low noise amplifier disposed on the module board; a transmission filter (a first acoustic wave filter) disposed on one of the first principal surface and the second principal surface; and a reception filter (a second acoustic wave filter) disposed on one of the first principal surface and the second principal surface. An absolute value of a temperature coefficient of frequency (TCF) of the transmission filter is smaller than an absolute value of a TCF of the reception filter, and a distance between the transmission filter and the power amplifier is shorter than a distance between the reception filter and the power amplifier.

Abstract: The disclosure provides a method and a device for multi-antenna transmission in a base station and a User Equipment (UE). The UE, in turn, receives a first higher-layer signaling, monitors a first-type physical layer signaling in a first radio resource pool, and receives second downlink information in a second radio resource pool. The first higher-layer signaling is used for determining first information and second information, and the first information is used for multi-antenna related receiving in the first radio resource pool. The first-type physical layer signaling is detected, and the first-type physical layer signaling is used for multi-antenna related receiving in the second radio resource pool, or, the first-type physical layer signaling is not detected, and the second information is used for multi-antenna related receiving in the second radio resource pool. The second radio resource pool is related to the first radio resource pool.

Abstract: In accordance with an embodiment, a method of operating a fractional-N phase locked loop (FN-PLL) includes: dividing a first clock signal using a multi-modulus divider (MMD) based on a modulus control signal to form a frequency-divided clock signal, where the first clock signal is based on an output clock of the PLL; generating the modulus control signal based on a divider control input value using a delta-sigma modulator (DSM); and when a fractional portion of the divider control input value is within a first range of values, and repeatedly removing a first number of clock cycles from the first clock signal before dividing the first clock signal using the MMD, where the first number of clock cycles is a non-integer number of clock cycles.

Abstract: A method, a computer-readable medium, and an apparatus are provided that enable use of a full transmission power for a UE having a first set of coherent antenna ports that is non-coherent to a second set of coherent antenna ports. The apparatus determines a transmission power for a data transmission from the UE to a base station based at least in part on power control signaling from the base station, determines at least one antenna port having non-zero data for transmission, and determines a transmission power split for the at least one antenna port. Then, the apparatus transmits the data transmission from the at least one antenna port, wherein a combined transmission power from the at least one antenna port corresponds to the transmission power determined based at least in part on the power control signaled from the base station.

Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

Abstract: A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.

Abstract: An operating method of an electronic device including a plurality of panel antennas and storing information about a plurality of codebooks includes: determining at least one panel antenna among the plurality of panel antennas based on environmental information; receiving control information from a base station; and selecting an optimal codebook among the plurality of codebooks based on the determined at least one panel antenna and the received control information.

Abstract: Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy.

Abstract: An apparatus includes a phase-locked loop and a jitter detection circuit. A method of detecting a jitter in the apparatus includes the phase-locked loop generating a lead control signal and a lag control signal according to a reference clock and a feedback clock, the jitter detection circuit generating a jitter signal according to the lead control signal and the lag control signal, the jitter detection circuit generating a jitter window signal according to the jitter signal, the jitter detection circuit identifying jitters in the clock signal according to the jitter signal and the jitter window signal, and the jitter detection circuit outputting a jitter indication signal according to the number of jitters identified.