Patents Examined by Prasith Thammavong
  • Patent number: 11403014
    Abstract: A request associated with one or more privileges assigned to a first entity may be received. Each of the one or more privileges may correspond to an operation of an integrated circuit. Information corresponding to the first entity and stored in a memory that is associated with the integrated circuit may be identified. Furthermore, the memory may be programmed to modify the information stored in the memory that is associated with the integrated circuit in response to the request associated with the one or more privileges assigned to the first entity.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 2, 2022
    Assignee: Cryptography Research, Inc.
    Inventors: Benjamin Che-Ming Jun, William Craig Rawlings, Ambuj Kumar, Mark Evan Marson
  • Patent number: 11397526
    Abstract: Systems, apparatuses, and methods related to media type selection for image data are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Image data inputs can be written (e.g., stored) in a particular type of memory media characteristics. For instance, selection of memory media can be based on one or more attributes of the image data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, image data from a first image sensor of a plurality of image sensors, identifying one or more attributes of the image data, and writing, based at least in part on the one or more attributes of the image data, the image data to a first memory media type of the plurality of memory media types.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zahra Hosseinimakarem, Bhumika Chhabra, Carla L. Christensen
  • Patent number: 11397677
    Abstract: One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek A. Sherlock, Gregg B. Lesartre
  • Patent number: 11392489
    Abstract: Mapping information management for data storage devices is provided. A controller caches write data issued by a host in a temporary storage and then programs the cached write data from the temporary storage to a non-volatile memory. The controller uses a mapping information format to manage mapping information of logical addresses recognized by the host. As presented in the mapping information format, the values not greater than a first threshold value and mapped to the configuration information storage space of the non-volatile memory are at least partially used to point to the temporary storage, and the values greater than the first threshold value are mapped to the non-volatile memory.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: July 19, 2022
    Assignee: SILICON MOTION, INC.
    Inventors: Ting-Han Lin, Che-Wei Hsu
  • Patent number: 11379381
    Abstract: A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Mi Seon Han, Yun Jeong Mun, Young Pyo Joo
  • Patent number: 11366751
    Abstract: A storage device includes a nonvolatile memory with physical blocks each including a plurality of clusters, and a controller that maintains a first table storing a relationship between a logical address and a physical address of the cluster, and a second table storing a relationship between a logical block and physical blocks allocated thereto. The controller performs garbage collection processing which includes copying data read from valid clusters of the first logical block to a destination logical block, creating a new logical block when the data read contains an uncorrectable error, allocating the physical blocks of the first logical block to the new logical block, and updating the second table so that the physical blocks of the first logical block are associated with the new logical block and no physical blocks are associated with the first logical block.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Tetsuya Yasuda
  • Patent number: 11360690
    Abstract: There is provided a storage device that is connected to a computer and receives an UNMAP command to cancel a relationship between a logical address and a physical address provided to the computer, in response to data deletion on the computer. The storage device includes a control unit configured to make data stored in a physical address specified by the UNMAP command irreversible.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 14, 2022
    Assignee: HITACHI, LTD.
    Inventors: Hirotaka Nakagawa, Akihiro Hara
  • Patent number: 11360893
    Abstract: A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventor: Seok-Jun Lee
  • Patent number: 11347635
    Abstract: A memory control method for a rewritable non-volatile memory module which includes a plurality of physical groups is provided according to an exemplary embodiment of the disclosure. The memory control method includes: storing first table information into a first physical group among the physical groups, wherein the first table information records management information corresponding to a first logical range; storing second table information into a second physical group among the physical groups, wherein the second table information also records the management information corresponding to the first logical range; and instructing a reading of the second table information from the second physical group to obtain the management information corresponding to the first logical range in response to that the first physical group is in a default status.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: May 31, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Jen Liang
  • Patent number: 11341047
    Abstract: A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 24, 2022
    Assignee: SATURN LICENSING LLC
    Inventor: Makiko Yamamoto
  • Patent number: 11340787
    Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, James A. Hall, Jr.
  • Patent number: 11314639
    Abstract: Garbage collection is performed for a virtualized storage system whose virtual address space is addressed in extents. Valid data in source extents is copied via a cache into destination extents. Once all valid data in a source extent is copied into one or more destination extents, the source extent may be reused. A source extent is released for reuse only after the one or more destination extents that received the valid data copied from the source extent are determined to be full, and the valid data copied from the source extent to the destination extent via the cache is flushed out of the cache.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roderick Guy Charles Moore, Miles Mulholland, William John Passingham, Richard Alan Bordoli
  • Patent number: 11307986
    Abstract: Systems and methods for dynamically placing data in a hybrid memory structure are provided. A machine learning (ML)-based, adaptive tiered memory system can actively monitor application memory to dynamically place the right data in the right memory tier at the right time. The memory system can use reinforcement learning to perform dynamic tier placement of memory pages.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 19, 2022
    Assignee: THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES
    Inventors: Adnan Maruf, Janki Bhimani, Ashikee Ghosh, Raju Rangaswami
  • Patent number: 11307781
    Abstract: Replicas of content can be managed in storage systems. In one example, a storage system can determine an amount of load on the storage system based on values for performance metrics indicating a performance of the storage system. Next, the storage system can determine that the storage system is to have a target number of replicas of content based on the amount of load on the storage system. The storage system can then adjust itself to have the target number of replicas of the content.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 19, 2022
    Assignee: Red Hat, Inc.
    Inventors: David Zafman, Brett Niver, Neha Ojha, Joshua Durgin, Adam Kupczyk
  • Patent number: 11307799
    Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 19, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Murong Lang, Zhenming Zhou
  • Patent number: 11301149
    Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: James Harris, Benjamin Walker, Tomasz Zawadzki
  • Patent number: 11269771
    Abstract: A storage device includes a nonvolatile memory including a main meta data area and a journal area, and a controller. The controller updates an address mapping table including a plurality of page mapping entries divided into a plurality of segments by executing a flash translation layer (FTL) stored in a working memory, stores updated page mapping entries of the plurality of page mapping entries in the journal area as journal data, and stores the plurality of segments, each having a size smaller than a physical page of the nonvolatile memory, in the main meta data area.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghoon Kim, Seonghun Kim
  • Patent number: 11256427
    Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Shivam Swami, Naveh Malihi, Anton Korzh, Glen E. Hush
  • Patent number: 11249908
    Abstract: An apparatus and method are disclosed for managing cache coherency. The apparatus has a plurality of agents with cache storage for caching data, and coherency control circuitry for acting as a point of coherency for the data by implementing a cache coherency protocol. In accordance with the cache coherency protocol the coherency control circuitry responds to certain coherency events by issuing coherency messages to one or more of the agents. A given agent is arranged, prior to entering a given state in which its cache storage is unused, to perform a flush operation in respect of its cache storage that may cause one or more evict messages to be issued to the coherency control circuitry. Further, once all evict messages resulting from performance of the flush operation has been issued, the given agent issues an evict barrier message to the coherency control circuitry.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: February 15, 2022
    Assignee: Arm Limited
    Inventors: Ole Henrik Jahren, Ian Rudolf Bratt, Sigurd Røed Scheistrøen
  • Patent number: 11249897
    Abstract: A data storage device includes a memory array including a plurality of memory cells; and a controller in communication with the memory array and configured to: store, in a map update buffer, one or more map segments including one or more logical address to be unmapped; determine, among logical address to physical address (L2P) entries of the one or more map segments stored in the map update buffer, L2P entries having the same memory block number; and selectively perform a first unmap operation or a second unmap operation according to whether all the L2P entries stored in the map update buffer have the same memory block number.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Ick Cho, Sung Kwan Hong, Byeong Gyu Park, Sung Hun Jeon