Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.

Abstract: A request to perform a first operation in a system that stores deduplicated data can be received. The system can include a data block stored at multiple logical address each referencing the data block. A reference count can be associated with the data block and can denote a number of logical addresses referencing the data block. Processing can be performed to service the request and perform the first operation, wherein the processing can include: acquiring a non-exclusive lock for a page that includes the reference count of the data block; storing, in a metadata log while holding the non-exclusive lock on the page, an entry to decrement the reference count of the data block; and releasing the non-exclusive lock on the page.

Abstract: The present disclosure generally relates to aborting a command efficiently using the host memory buffer (HMB). The command contains pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

Abstract: Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. A memory device may monitor a parameter of a component of the memory device or the memory device overall, and may determine whether the parameter satisfies a threshold. The parameter may represent or be associated with a lifetime of the component, a level of wear of the component, or an operating parameter violation of the component, or any combination thereof. The memory device may communicate, to a host device, an indication of the parameter satisfying the threshold, and the host device may use the information in the indication to adjust one or more parameters associated with operating the memory device, among other example operations.

Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

Abstract: A technique maintains online access to data stored in a plurality of storage devices during a hardware upgrade in which the plurality of storage devices moves between storage processor enclosures. The technique involves providing, from the plurality of storage devices, online access to the data while each storage device of the plurality of storage devices resides in a first storage processor enclosure. The technique further involves providing, from the plurality of storage devices, online access to the data while the plurality of storage devices is moved from the first storage processor enclosure to a second storage processor enclosure (e.g., transferring each storage devices one by one before triggering a rebuild process). The technique further involves providing, from the plurality of storage devices, online access to the data while each storage device of the plurality of storage devices resides in the second storage processor enclosure.

Abstract: A system, method, and machine-readable storage medium for retrieving data are provided. In some embodiments, a cache may receive a request for data from a client. The cache may determine that a first subset of the data is stored on a storage device and that a second subset of the data is stored at a cloud address located at a cloud storage endpoint. The cache may also receive from the storage device the first subset of data. The cache further receives from the cloud storage endpoint the second subset of data in response to transmitting a request for the second subset of data stored at the cloud address to the cloud storage endpoint. The cache then transmits to the client the first and second subsets of data from the various sources in response to the data request.

Abstract: A system including a fabric manager, a memory mapper, and a switch is described. The memory mapper receives and stores mapping information from the fabric manager that maps memory locations in a plurality of hosts to corresponding memory locations in a plurality of physical devices. The switch receives at least a portion of the mapping information from the memory mapper, receives a request from a host, and accesses memory that is identified by the request on a physical device of the plurality of physical devices.

Abstract: Managing storage device evacuation that includes a plurality of storage devices, including: detecting, by the storage system, an occurrence of a storage device evacuation event associated with a source storage device within a write group, wherein the write group is a subset of storage devices storing a data set; responsive to detecting the occurrence of the storage device evacuation event, identifying, by the storage system, a target storage device for receiving data stored on the source storage device; and migrating, by the storage system, the data stored on the source storage device to the target storage device.

Abstract: Systems and methods are provided for prioritizing system memory for separate isolated computing workspaces (e.g., cloud-based software containers) that are executing together on an information handling system by reallocating higher performance system memory to higher-ranked computing workspace/s. In one example, the disclosed systems and methods may be implemented to optimize system memory usage for memory-heavy heterogeneous workloads of workspaces that are simultaneously executing together as modern clients on an information handling system.

Abstract: Embodiments for a metadata predictor. An index pipeline generates indices in an index buffer in which the indices are used for reading out a memory device. A prediction cache is populated with metadata of instructions read from the memory device. A prediction pipeline generates a prediction using the metadata of the instructions from the prediction cache, the populating of the prediction cache with the metadata of the instructions being performed asynchronously to the operating of the prediction pipeline.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device is operable to receive a memory access request for a data object stored within the DSN, determine a realm for the memory access request, determine an authorization service for the realm and generate an authorization request for the memory access request. The computing device is further operable to transmit the authorization request to an authorization service, receive an authorization request response from the authorization service, determine whether the memory access request is authorized and process the memory access request.

Abstract: An operation method of a storage device includes receiving a first write request; adding the first write request to a first fragment; selecting at least “n” (e.g., at least two) streams among a plurality of pre-allocated streams when a size of the first fragment, when a size of the first fragment is >=a reference value, based on a cosine similarity between the first fragment and each of the pre-allocated streams; applying input information to a machine learning model to detect a first sequential stream associated with the first fragment from among the at least “n” streams; allocating a stream identifier of the first sequential stream to the first fragment; and storing write data included in the first fragment based on the stream identifier of the first sequential stream. The input information includes statistical information of at least one of the “n” streams and the first fragment.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

Abstract: Techniques are described herein processing asynchronous power transition events while maintaining a persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush prior to invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure all resets and power-transitions requested in hardware reliably complete within a bounded window of time independent of whether the persistent cache flush handler succeeds.

Abstract: Processing a read request to read metadata from an entry of a metadata page may include: determining whether the metadata page is cached; responsive to determining the metadata page is cached, obtaining the first metadata from the cached metadata page; responsive to determining the metadata page is not cached, determining whether the requested metadata is in a metadata log of metadata changes stored in a volatile memory; and responsive to determining the metadata is the metadata log of metadata changes stored in the volatile memory, obtaining the requested metadata from the metadata log. Processing a write request that overwrites an existing value of a metadata page with an updated value may include: recording a metadata change in the metadata log that indicates to update the metadata page with the updated value; and performing additional processing during destaging that uses the existing value prior to overwriting it with the updated value.

Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.