Patents Examined by Prasith Thammavong
  • Patent number: 11656982
    Abstract: Various embodiments disclosed herein are related to a non-transitory computer readable storage medium. In some embodiments, the medium includes instructions stored thereon that, when executed by a processor, cause the processor to send an indication of a first storage location to a destination host. In some embodiments, the first storage location includes content that is swapped out from a memory location in a source host. In some embodiments, the indication includes one or more of a logical address and a first physical address. In some embodiments, the medium includes instructions stored thereon that, when executed by a processor, cause the processor to map the logical address of the first storage location to a second physical address of a second storage location. In some embodiments, the destination host accesses the content of the first storage location.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: May 23, 2023
    Assignee: Nutanix, Inc.
    Inventors: Carl Alan Waldspurger, Felipe Franciosi, Florian Anselm Johannes Schmidt
  • Patent number: 11650920
    Abstract: A storage control system maintains a write cache in a non-volatile memory device of primary memory of a storage node. The write cache comprises a cyclic buffer and pointers to manage the write cache and track a tail location and head location of the write cache. The storage control system receives a write request from a host system, which comprises a data item to be written to primary storage. The received data item is written together with an associated metadata item at the head location of the write cache. The items in the write cache are arranged in a cyclic write order from the tail location to the head location. The storage control system sends an acknowledgment to the host system that the data item is successfully written to the primary storage, in response to the received data item and the associated metadata item being stored in the write cache.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 16, 2023
    Assignee: Dell Products L.P.
    Inventors: Yosef Shatsky, Doron Tal
  • Patent number: 11625327
    Abstract: Embodiments of the present disclosure relate to cache memory management. Based on anticipated input/output (I/O) workloads, at least one or more of: sizes of one or more mirrored and un-mirrored caches of global memory and their respective cache slot pools are dynamically balanced. Each of the mirrored/unmirrored caches can be segmented into one or more cache pools, each having slots of a distinct size. Cache pool can be assigned an amount of the one or more cache slots of the distinct size based on the anticipated I/O workloads. Cache pools can be further assigned the amount of distinctly sized cache slots based on expected service levels (SLs) of a customer. Cache pools can also be assigned the amount of the distinctly sized cache slots based on one or more of predicted I/O request sizes and predicted frequencies of different I/O request sizes of the anticipated I/O workloads.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 11, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: John Krasner, Ramesh Doddaiah
  • Patent number: 11611617
    Abstract: A method to build a persistent memory (PM)-based data storage system without involving a processor (CPU) at storage nodes is disclosed which includes storing data in one or more storage nodes that only include PM and no CPUs, with data stored in PM in form of link lists, accessing data stored in the one or more storage nodes' PM directly by remote compute nodes through a network, maintaining metadata associated with the data by one or more global controllers (metadata servers), upon request by a user to read or write data, the compute nodes contacting the one or more metadata servers to obtain location of data of interest in form of pointers (shortcuts), and the compute nodes sending network requests directly to the one or more storage nodes' PM to locate latest version of data by tracing the link list from the associated shortcut to corresponding tails.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 21, 2023
    Assignee: Purdue Research Foundation
    Inventors: Yiying Zhang, Shin-Yeh Tsai
  • Patent number: 11592999
    Abstract: The storage part receives an I/O request including the ID of software, information regarding a storage area to and from which the software performs input and output, and a token. The storage part checks the I/O request against the software ID, the information regarding the storage area, and the token received from an I/O control part so as to determine whether access to the storage part is allowed. Upon determination that the access to the storage part is allowed, the storage part processes the I/O request.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: February 28, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Hirai, Takahiro Yamamoto, Hiroto Ebara, Masakuni Agetsuma, Yoshinori Ohira
  • Patent number: 11579791
    Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jeffery J. Leyda, Nathan A. Eckel
  • Patent number: 11580022
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a sort/no-sort determination is made prior to issuing to a write command to a target storage controller. The write command identifies a write data unit such track write data, for example, of a first write list of write data units to be written to storage locations of storage. The write command further identifies the storage location at which the write data unit of the first write list is to be stored. In one embodiment, the sort/no-sort determination determines whether an insertion point for an entry in a target write list is to be determined as a function of a write list search such as a logarithmic time search for a write list sort. As a result, the write list search for a write list sort, may be selectively either performed or bypassed for insertion of the target write list entry as a function of the sort/no-sort determination Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Hatfield, Lokesh Mohan Gupta, Matthew G. Borlick
  • Patent number: 11567696
    Abstract: The present disclosure discloses a control device of data storage system, including a host interface, a peer interface, a storage unit interface, a processor and a local data management module. The host interface is connected and communicated with a storage server for data interaction with the storage server. The peer interface is configured for data communication connection with a storage unit of an adjacent control device in the data storage system. The storage unit interface is configured to connect a storage unit. The local data management module is configured for local data management of the data in the storage unit according to the data management instruction via the processor. The host interface is configured to send result data of local data management to the storage server.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 31, 2023
    Assignee: SHENZHEN DAPU MICROELECTRONICS CO., LTD.
    Inventors: Jing Yang, Haibo He, Qing Yang
  • Patent number: 11567867
    Abstract: A controller controls a memory device. The controller includes a buffer buffering one or more data chunks received from a host until the one or more data chunk is stored in the memory device, and a processor sorting and storing, according to data types of the one or more data chunks, the one or more data chunks buffered in the buffer in a plurality of memory regions of the memory device in a normal operation, the plurality of memory regions respectively corresponding to a plurality of data types. In response to a sudden power-off (SPO), the processor generates map data indicating a relationship between the one or more data chunks and the plurality of memory regions, generates a data string by merging the one or more data chunks, and stores the data string and the map data in a temporal memory region of the memory device.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Hungyung Cho
  • Patent number: 11567868
    Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11561717
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data, and the updated delta data is copied to the RAM2. The delta data stored in the RAM2 is copied to the storage unit periodically. The controller tracks which delta data has been copied to the RAM2 and to the storage unit. During a power failure, the delta data and the change log data are copied from the RAM1 or the RAM2 to the storage unit.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 24, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Peter Grayson
  • Patent number: 11556464
    Abstract: A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngmoon Kim, Dong-Min Kim, Jeong-Woo Park
  • Patent number: 11550711
    Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, Nadav Grosz, Qing Liang, David Aaron Palmer
  • Patent number: 11550669
    Abstract: One example method includes receiving data segments that are not already part of a full disk image of a backup, storing the data segments in storage, determining whether or not an aggregate total of data segments in the storage, that are not already part of a full disk image of a backup, equals or exceeds a threshold, when the aggregate total of data segments in the storage equals or exceeds the threshold, creating a full disk image of a backup that includes the data segments in storage, and storing the created full disk image of the backup to a recovery disk.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 10, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Assaf Natanzon, David Zlotnick, Boris Shpilyuck
  • Patent number: 11520704
    Abstract: A load-store unit (LSU) of a processor core determines whether or not a second store operation specifies an adjacent update to that specified by a first store operation. The LSU additionally determines whether the total store data length of the first and second store operations exceeds a maximum size. Based on determining the second store operation specifies an adjacent update and the total store data length does not exceed the maximum size, the LSU merges the first and second store operations and writes merged store data into a same write block of a cache. Based on determining that the total store data length exceeds the maximum size, the LSU splits the second store operation into first and second portions, merges the first portion with the first store operation, and writes store data of the partially merged store operation into the write block.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Cordes, Bryan Lloyd
  • Patent number: 11520495
    Abstract: An image forming apparatus includes a solid state drive (SSD) that stores information, a Serial Advanced Technology Attachment (SATA) controller that reads information from the SSD, writes information to the SSD, and transmits a device sleep (DEVSLP) signal for shifting the SSD to a DEVSLP state, and a power source control unit that can stop power to the SATA controller and transmits the DEVSLP signal for shifting the SSD to the DEVSLP state during a period in which the power to the SATA controller is stopped.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 6, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Minoru Hashimoto
  • Patent number: 11513708
    Abstract: Disclosed deduplication techniques at a distributed data storage system guarantee that space reclamation will not affect deduplicated data integrity even without perfect synchronization between components. By understanding certain “behavioral” characteristics and schedule cadences of backup operations that generate backup copies received at the distributed data storage system, data blocks that are not re-written by subsequent backup copies are pro-actively aged, while promoting continued retention of data blocks that are re-written. An expiry scheme operates with block-level granularity. Each unique deduplicated data block is given an expiry timeframe based on the block's arrival time at the distributed data storage system (i.e., when a backup copy supplies the block) and further based on backup frequencies of the various virtual disks referencing a unique system-wide identifier of the block, which is based on the block's hash value. Communications between components are kept to an as-needed basis.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 29, 2022
    Assignee: Commvault Systems, Inc.
    Inventors: Bharat Pundalik Naik, Xiangyu Wang, Avinash Lakshman
  • Patent number: 11513972
    Abstract: Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: November 29, 2022
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Tianshi Chen, Qi Guo, Yunji Chen
  • Patent number: 11507508
    Abstract: The present disclosure generally relates to improving write cache utilization by recommending a time to initiate a data flush operation or predicting when a new write command will arrive. The recommending can be based upon considerations such as a hard time limit for data caching, rewarding for filling the cache, and penalizing for holding data for too long. The predicting can be based on tracking write command arrivals and then, based upon the tracking, predicting an estimated arrival time for the next write command. Based upon the recommendation or predicting, the write cache can be flushed or the data can remain in the write cache to thus more efficiently utilize the write cache without violating a hard stop time limit.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon
  • Patent number: 11507511
    Abstract: Techniques for storing data involve estimating a hit ratio of a digest cache associated with a target storage device, the digest cache recording a digest of data that is stored in the target storage device after preprocessing; generating, according to a determination that the hit ratio is lower than a predetermined threshold, a digest for target data to be stored and performing the preprocessing; and storing, according to a determination that the digest of the target data is missing in the digest cache, the preprocessed target data in the target storage device, and recording the digest of the target data in the digest cache. Such techniques can achieve good system performance in both cases of high data repetition and low data repetition.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Leihu Zhang, Chen Gong, Shuo Lv