Abstract: Disclosed deduplication techniques at a distributed data storage system guarantee that space reclamation will not affect deduplicated data integrity even without perfect synchronization between components. By understanding certain “behavioral” characteristics and schedule cadences of backup operations that generate backup copies received at the distributed data storage system, data blocks that are not re-written by subsequent backup copies are pro-actively aged, while promoting continued retention of data blocks that are re-written. An expiry scheme operates with block-level granularity. Each unique deduplicated data block is given an expiry timeframe based on the block's arrival time at the distributed data storage system (i.e., when a backup copy supplies the block) and further based on backup frequencies of the various virtual disks referencing a unique system-wide identifier of the block, which is based on the block's hash value. Communications between components are kept to an as-needed basis.

Abstract: The present disclosure generally relates to aborting a command efficiently using the host memory buffer (HMB). The command contains pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

Abstract: A memory system includes a memory medium and a memory controller configured to control the memory medium. The memory controller includes a training core and a training block. The training core is configured to detect a delay time of a clock signal to generate a delay selection signal during a training operation for the memory medium. The training block is configured to generate a delayed clock signal which is delayed by a time period set according to the delay selection signal outputted from the training core.

Abstract: A method, a device, and a computer program product for creating a stripe in a storage system. In the method, a balance index of a storage device in multiple storage devices in the storage system is determined. Here, the balance index indicates a relationship between the state distribution of a set of stripes which have been allocated for use in the storage device and the state distribution of a set of stripes which have been allocated for use in the multiple storage devices. An influence factor for the balance index of the storage device in the multiple storage devices is determined according to attributes of the storage device in the multiple storage devices. A storage device for creating a stripe is selected from the multiple storage devices based on the determined balance index and the determined influence factor. One extent in the selected storage device is added to the stripe.

Abstract: In a multi-node storage system, a node's capacity has an upper limit, and capacities provided by nodes are smaller than a capacity of a global pool. A volume having a capacity larger than the capacity of one node is created by the node. A write error occurs when an amount of data larger than the capacity of the node is written. A storage system reduces the frequency of such a write error. A global pool is based on a plurality of local pools of a plurality of storage nodes that constitute a node group. In any of the storage nodes, a capacity relationship is maintained where a used capacity of a volume created by the storage node is equal to or less than an available capacity of a local pool of the storage node. A storage management unit manages the node group and selects the storage node.

Abstract: A system includes a non-volatile memory (NVM), and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone index; and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index for an active zone, wherein the zone write pointer includes a location in the LBA space for the active zone; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; and journal metadata of the entry of one the ZMDS or the HFUT affected by a flush transition between the ZMDS and the HFUT.

Abstract: There are provided a memory controller for managing meta data and an operating method of the memory controller. The memory controller includes: a buffer memory for storing meta data used to control an operation of a memory device; and a central processing unit for updating the meta data stored in the buffer memory whenever the operation of the memory device is controlled. The central processing unit may transmit the meta data stored in the buffer memory to a host at a first frequency, and transmit the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive a memory access request, wherein the memory access request is associated with a data set. The apparatus may include a non-volatile memory storage circuit configured to create and store a transformed data set. The apparatus may include a translation circuit comprising at least one machine learning circuit. The translation circuit may be configured to: in response to a write memory access, convert an original version of the data set to the transformed data set, and in response to a read memory access, convert the transformed data set to a reconstructed data set.

Abstract: Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.

Abstract: A method includes receiving a request for a cache operation at a first storage device and identifying at least a first input/output operation at a first data block at the first storage device, the first data block having a corresponding first data range. The method also includes identifying a second input/output operation at a second data block having a corresponding second data range and initiating a read operation at the first storage device that comprises the first data block and the second data block. The method further includes combining the first data block and the second data block into a first data volume and writing the first data volume to a second storage device as a third input/output operation.

Abstract: A memory controller maintains a mapping of target ranges in system memory space interleaved two-ways across locations in a three-rank environment. For each range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks. At least one of the ranges has offsets that differ relative to each other. Such offsets allow the three ranks to be fully interleaved, two ways. An instruction to read data at a rank-agnostic location in the diverse-offset range causes the memory controller to map the rank-agnostic location to two interleaved locations offset different amounts from their respective base locations in their ranks. The controller may then affect the transfer of the data at the two interleaved locations.

Abstract: A method includes determining, by a computing device of a plurality of computing devices of a storage network, a data processing plan for processing an access request. The method further includes identifying two or more processing units of a plurality of processing units of the storage network based on the data processing plan and availability information, and determining processing capabilities of each of the two or more processing units. The method further includes selecting a processing unit of the two or more processing units to process the access request based on a favorable comparison of the processing capabilities of the processing unit and the data processing plan. The method further includes selecting one or more processing options of the processing unit to process the access request according to the data processing plan, and sending the access request and selection of the one or more processing options to the processing unit.

Abstract: A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.

Abstract: A request associated with one or more privileges assigned to a first entity may be received. Each of the one or more privileges may correspond to an operation of an integrated circuit. Information corresponding to the first entity and stored in a memory that is associated with the integrated circuit may be identified. Furthermore, the memory may be programmed to modify the information stored in the memory that is associated with the integrated circuit in response to the request associated with the one or more privileges assigned to the first entity.

Abstract: Systems, apparatuses, and methods related to media type selection for image data are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Image data inputs can be written (e.g., stored) in a particular type of memory media characteristics. For instance, selection of memory media can be based on one or more attributes of the image data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, image data from a first image sensor of a plurality of image sensors, identifying one or more attributes of the image data, and writing, based at least in part on the one or more attributes of the image data, the image data to a first memory media type of the plurality of memory media types.

Abstract: One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

Abstract: Mapping information management for data storage devices is provided. A controller caches write data issued by a host in a temporary storage and then programs the cached write data from the temporary storage to a non-volatile memory. The controller uses a mapping information format to manage mapping information of logical addresses recognized by the host. As presented in the mapping information format, the values not greater than a first threshold value and mapped to the configuration information storage space of the non-volatile memory are at least partially used to point to the temporary storage, and the values greater than the first threshold value are mapped to the non-volatile memory.

Abstract: A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.

Abstract: A storage device includes a nonvolatile memory with physical blocks each including a plurality of clusters, and a controller that maintains a first table storing a relationship between a logical address and a physical address of the cluster, and a second table storing a relationship between a logical block and physical blocks allocated thereto. The controller performs garbage collection processing which includes copying data read from valid clusters of the first logical block to a destination logical block, creating a new logical block when the data read contains an uncorrectable error, allocating the physical blocks of the first logical block to the new logical block, and updating the second table so that the physical blocks of the first logical block are associated with the new logical block and no physical blocks are associated with the first logical block.