Patents Examined by Quoc D. Hoang
  • Electroluminescent device with improved luminous efficiency and viewing angle and method of manufacturing the same
    Patent number: 11322563
    Abstract: Described is an electroluminescent device including an array substrate having a thin-film transistor formed thereon, an organic insulating layer formed on the array substrate having the thin-film transistor formed thereon, barriers disposed on the organic insulating layer, an anode formed on the organic insulating layer between the barriers to thus be electrically connected to the thin-film transistor and configured to cover at least a portion of the barriers, a light-emitting layer formed on the anode, and a cathode formed on the light-emitting layer, thus exhibiting superior emission efficiency and a wide viewing angle. A method of making or manufacturing the electroluminescent device is also described.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: May 3, 2022
    Assignee: Dongwoo Fine-Chem Co., Ltd.
    Inventors: Hun-Sik Kim, Jong-Soo Lee
  • Display unit, display unit manufacturing method and organic light emitting diode display device with desiccants
    Patent number: 11302756
    Abstract: A display unit, a display unit manufacturing method, and an organic light emitting diode display device are provided. The display unit includes: a substrate; a thin film transistor layer disposed above the substrate; an anode metal layer disposed above the thin film transistor layer; a pixel definition layer disposed above the anode metal layer; a light emitting structure disposed above the pixel definition layer. The pixel definition layer includes a first lamination layer and a second lamination layer disposed above the first lamination layer. Desiccants are distributed evenly in the second lamination layer.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: April 12, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ming Xiang, Shoucheng Wang
  • Semiconductor device including a fuse latch for latching data of a repair fuse cell
    Patent number: 11302633
    Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Duk Su Chun
  • Semiconductor package substrate with a smooth groove about a perimeter of a semiconductor die
    Patent number: 11302652
    Abstract: A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ChienHao Wang, Bob Lee, YuhHarng Chien
  • Fan-out multi-device hybrid integrated flexible micro system and fabrication method thereof
    Patent number: 11296033
    Abstract: The invention discloses a fan-out multi-device hybrid integrated flexible micro-system and an associated fabrication method in the field of microelectronics. The flexible microsystem uses microelectromechanical system (MEMS) chips and/or integrated circuit (IC) chips as the device units, flexible isolation trenches filled with flexible polymer as a flexible connection between the device units, and metal wiring layers to provide electrical interconnections between the device units. The disclosed multi-device hybrid integrated flexible micro-system completed by a fan-out method not only retains excellent electrical performance of silicon-based devices, but also realizes flexibility of the overall micro-system, and has stable structure and reliable performance.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 5, 2022
    Assignee: Peking University
    Inventors: Wei Wang, Xiao Dong
  • Organic light emitting diode including convex curve or concave curve and organic light emitting device including the same
    Patent number: 11289683
    Abstract: Provided are an organic light-emitting diode (OLED) and an organic light-emitting device including the same. The OLED includes a first electrode, an organic emissive layer which includes a plurality of convex curves or a plurality of concave curves in a light-emitting region and of which a slope of an inclined plane of an upper region with respect to a horizontal line dividing a height of the plurality of convex curves into halves is greater than a slope of an inclined plane of a lower region thereof, and a second electrode provided on the organic emissive layer. Accordingly, the OLED and the organic light-emitting device including the same are capable of improving current efficiency.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 29, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Ji-Hyang Jang, So-Young Jo, Won-Hoe Koo
  • Semiconductor device with composite landing pad for metal plug
    Patent number: 11282790
    Abstract: The present disclosure relates to a semiconductor device with a composite landing pad. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed over the lower metal plug, and an outer silicide portion disposed over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: March 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Cheng Liao
  • Semiconductor device package having a core substrate and an embedded component in the core substrate
    Patent number: 11276660
    Abstract: A semiconductor device package includes an electronic component, a first passivation layer having an inner surface surrounding the electronic component, and a conductive layer disposed on the inner surface of the first passivation layer. The electronic component has a first surface, a second surface opposite the first surface, and a lateral surface extended between the first surface and the second surface. The conductive layer has a relatively rough surface. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chih Cheng Lee
  • Film formation apparatus configured to supply mist of a solution to surface of a substrate and method of manufacturing semiconductor device using the film formation apparatus
    Patent number: 11270882
    Abstract: A film formation apparatus is configured to supply mist of a solution to a surface of a substrate so as to epitaxially grow a film on the surface of the substrate. The film formation apparatus may be provided with: a furnace configured to house and heat the substrate; a reservoir configured to store the solution; a heater configured to heat the solution in the reservoir; an ultrasonic transducer configured to apply ultrasound to the solution in the reservoir so as to generate the mist of the solution in the reservoir; and a mist supply path configured to carry the mist from the reservoir to the furnace.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 8, 2022
    Assignees: DENSO CORPORATION, NATIONAL UNIVERSITY CORPORATION KYOTO INSTITUTE OF TECHNOLOGY
    Inventors: Tatsuji Nagaoka, Hiroyuki Nishinaka, Daisuke Tahara, Masahiro Yoshimoto
  • Conductive diffuser and manufacturing method of the same
    Patent number: 11264243
    Abstract: A diffuser includes a diffuser element made of silicon carbide having conductivity, conductive holding members for holding the diffuser element, conductive gaskets that seal between the diffuser element and the holding members. Static electricity on the diffuser element is eliminated through the gaskets, and the holding members.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 1, 2022
    Assignee: COORSTEK KK
    Inventor: Hiroki Watanabe
  • Interposer board without feature layer structure and method for manufacturing the same
    Patent number: 11257713
    Abstract: A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Min Gu, Benxia Huang, Lei Feng, Bingsen Xie
  • Through wafer trench isolation between transistors in an integrated circuit
    Patent number: 11251138
    Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Thomas Dyer Bonifield, Sreeram Subramanyam Nasum, Peter Smeys, Benjamin Stassen Cook
  • Power semiconductor module for improved heat dissipation and power density, and method for manufacturing the same
    Patent number: 11251116
    Abstract: The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 15, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hamit Duran, Junfu Hu
  • Film forming method and heat treatment apparatus
    Patent number: 11239076
    Abstract: A film forming method includes forming an amorphous semiconductor film on a recess, forming a first polycrystalline semiconductor film by performing heat treatment on the amorphous semiconductor film, and forming a second polycrystalline semiconductor film on the first polycrystalline semiconductor film formed by the heat treatment.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: February 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yutaka Motoyama, Hiroyuki Hayashi
  • Method and apparatus for laser drilling blind vias
    Patent number: 11232951
    Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 25, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei-Sheng Lei, Kurtis Leschkies, Roman Gouk, Steven Verhaverbeke, Visweswaren Sivaramakrishnan
  • Embedded multi-die interconnect bridge having a molded region with through-mold vias
    Patent number: 11233009
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Praneeth Kumar Akkinepally, Frank Truong, Jason M. Gamba, Robert Alan May
  • Method of optimizing film deposition process in semiconductor fabrication by using gas sensor
    Patent number: 11232946
    Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Rei-Lin Chu, Chih-Ming Chen, Chung-Yi Yu, Yeur-Luen Tu
  • Methods for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition process in a reaction chamber
    Patent number: 11227763
    Abstract: A method for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition in a reaction chamber is disclosed. The method may include: depositing a hafnium oxide film on the substrate utilizing a first sub-cycle of the cyclical deposition process and depositing a lanthanum oxide film utilizing a second sub-cycle of the cyclical deposition process.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 18, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Tatiana Ivanova, Perttu Sippola, Michael Eugene Givens
  • Chip-on-chip power card with embedded thermal conductor
    Patent number: 11227821
    Abstract: Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame and a P lead frame, each having a body portion and a terminal portion. The power card includes an O lead frame having a body portion and a cooling portion. The power card includes a first power device located between the body portion of the N lead frame and the body portion of the O lead frame. The power card includes a second power device located between the body portion of the O lead frame and the body portion of the P lead frame, the O lead frame configured to receive heat from the first power device and the second power device by the body portion of the O lead frame and transfer the heat to the cooling portion of the O lead frame for heat dissipation.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: January 18, 2022
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Feng Zhou
  • Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures
    Patent number: 11227849
    Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Srinivas V. Pietambaram, Kristof Darmawikarta, Gang Duan, Sameer Paital