Abstract: Provided are an organic light-emitting diode (OLED) and an organic light-emitting device including the same. The OLED includes a first electrode, an organic emissive layer which includes a plurality of convex curves or a plurality of concave curves in a light-emitting region and of which a slope of an inclined plane of an upper region with respect to a horizontal line dividing a height of the plurality of convex curves into halves is greater than a slope of an inclined plane of a lower region thereof, and a second electrode provided on the organic emissive layer. Accordingly, the OLED and the organic light-emitting device including the same are capable of improving current efficiency.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

Abstract: Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.

Abstract: A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.

Abstract: In one example, a semiconductor device comprises a substrate comprising a conductive structure, an electronic component over a top side of the substrate and electrically coupled with the conductive structure, a lid structure over the substrate and over the electronic component, and a vertical interconnect in the lid structure extending to a top surface of the lid structure and electrically coupled with the conductive structure. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die cavity with a die attached therein. The package substrate also includes a cavity for bonding a cap thereto to form a hermetic package. The cap is bonded to the cavity using sealing rings.

Abstract: A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.

Abstract: A method for depositing a hafnium lanthanum oxide film on a substrate by a cyclical deposition in a reaction chamber is disclosed. The method may include: depositing a hafnium oxide film on the substrate utilizing a first sub-cycle of the cyclical deposition process and depositing a lanthanum oxide film utilizing a second sub-cycle of the cyclical deposition process.

Abstract: A semiconductor device includes first and second dielectric fins disposed above a substrate, a semiconductor channel layer sandwiched between the first and second dielectric fins, a gate structure engaging the semiconductor channel layer, a source/drain (S/D) feature abutting the semiconductor channel layer and sandwiched between the first and second dielectric fins, and an air gap sandwiched between the first and second dielectric fins. The air gap exposes a first sidewall of the S/D feature facing the first dielectric fin and a second sidewall of the S/D feature facing the second dielectric fin.

Abstract: A display apparatus includes a display panel module including a front surface displaying an image and a rear surface opposite the front surface, and a heat dissipation member disposed on the rear surface of the display panel module and including a first portion, that is in contact with the display panel module, and a second portion that is spaced farther apart from the display panel module than the first portion is. The heat dissipation member includes at least one portion that is bent between the first portion and the second portion with respect to a bending axis parallel to the rear surface.

Abstract: A method of processing a substrate includes loading the substrate to which a processing liquid is adhered, inside a processing container, removing the processing liquid adhering to the substrate by supplying a first organic solvent to the loaded substrate, causing the substrate to be water-repellent by supplying a water repellent to the substrate from which the processing liquid has been removed, supplying a second organic solvent to the water-repellent substrate, and drying the substrate by volatilizing the second organic solvent adhering to the substrate.

Abstract: A semiconductor wafer has a semiconductor body, an insulation layer on the semiconductor body, a scribeline region designated to be subjected to a wafer separation processing stage, and an optically detectable reference feature laterally spaced inward from the scribeline region and configured to serve as a reference position during the wafer separation processing stage. A corresponding method of processing the semiconductor wafer, a power semiconductor die and a semiconductor wafer separation apparatus are also described.

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate. The semiconductor device structure also includes a gate dielectric layer formed between the gate electrode layer and the semiconductor substrate. In addition, the semiconductor device structure includes a first gate spacer having a hydrophobic surface that covers a first sidewall of the gate electrode layer. The first sidewall of the gate electrode layer extends along a first sidewall of the gate dielectric layer, so that the first sidewall of the gate dielectric layer is separated from the hydrophobic surface of the first gate spacer.

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: An optoelectronic device comprises an epitaxial stack, comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a trench exposing a portion of the first semiconductor layer; a first insulating layer formed on a side wall of the trench to electrically insulate from the active layer and the second semiconductor layer; a first electrode formed on the trench; a second electrode formed on the second semiconductor layer; a supporting device covering the epitaxial stack; an optical layer covering the first electrode and the second electrode, comprising a plurality of openings corresponding to positions of the first electrodes and the second electrodes; a fifth electrode electrically connected with the first electrode; and a sixth electrode electrically connected with the second electrode, wherein the fifth electrode and the sixth electrode each comprises a side comprising a length longer that of an edge of the epitaxial stack.