Abstract: A laser irradiation apparatus includes: a laser generation apparatus configured to generate first laser light for performing heat treatment of an object to be processed; a measurement-laser emission unit configured to emit linearly-polarized second laser light toward an irradiation area on the object to be processed to which the first laser light is applied; a first polarizing plate configured to let, of the whole reflected light of the second laser light reflected by the object to be processed, a part of the reflected light that has a first polarization direction pass therethrough; and a measurement-laser detection unit configured to detect the reflected light that has passed through the first polarizing plate.

Abstract: A method of fabricating a wiring board with an embedded interposer substrate includes preparing a main substrate, forming a recess on the main substrate, placing an interposer substrate into the recess, electrically connecting a second pad of the interposer substrate and the first pad of the main substrate, and filling a gap between the interposer substrate and the main substrate with an underfill. The recess exposes a first pad of the main substrate. A second pad of interposer substrate and the first pad of the main substrate are made of the same metal and formed in different outer surface profiles. The underfill entirely touches side surfaces and a bottom surface of the interposer substrate.

Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

Abstract: A method for manufacturing a semiconductor device includes at least the following three steps: (A) A step of preparing a structure including a semiconductor wafer having a circuit-formed surface and an adhesive film attached to the circuit-formed surface side of the semiconductor wafer; (B) A step of back grinding a surface on a side opposite to the circuit-formed surface side of the semiconductor wafer; and (C) A step of radiating ultraviolet rays to the adhesive film and then removing the adhesive film from the semiconductor wafer. The adhesive film includes a base material layer and an ultraviolet-curable adhesive resin layer provided on one surface side thereof. The adhesive resin layer includes an ultraviolet-curable adhesive resin, and a saturated electrostatic potential V1 of a surface of the adhesive resin layer after ultraviolet curing, which is measured using a specific method, is equal to or less than 2.0 kV.

Abstract: Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.

Abstract: A dividing apparatus includes a table having a transparent plate having a holding surface for holding a workpiece thereon and a lower illumination unit for illuminating the holding surface from below, a first storage section for storing a first image including a white portion where illumination light from the lower illumination unit is transmitted through the workpiece and displayed as white and a black portion where the illumination light is blocked by the workpiece and displayed as black when an image of a kerf defined by a dividing unit in the workpiece held on the holding surface is captured by an image capturing unit with the lower illumination unit being energized, and a white pixel detecting section for detecting whether or not there are pixels in the white portion of the first image in directions perpendicular to directions along which a street extends.

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.

Abstract: A package structure is provided. The package structure includes a substrate having a first surface and a second surface opposite the first surface. The substrate includes a cavity extending from the second surface toward the first surface, and thermal vias extending from a bottom surface of the cavity to the first surface. The package structure also includes at least one electronic device formed in the cavity and thermally coupled to the thermal vias. In addition, the package structure includes an insulating layer formed over the second surface and covering the first electronic device. The insulating layer includes a redistribution layer (RDL) structure electrically connected to the electronic device. The package structure also includes an encapsulating material formed in the cavity, extending along sidewalls of the electronic device and between the electronic device and the insulating layer.

Abstract: An object is to provide a technique capable of improving heat dissipation while maintaining the workability of a product in a semiconductor device. A semiconductor device includes power chips, control chips configured to control the power chips, power side terminals, control side terminals, and a mold resin covering the power chips, the control chips, one ends side of the power side terminals, and one ends side of the control side terminals. An other ends side of the power side terminals and an other ends side of the control side terminals protrude horizontally from a side surface of the mold resin and bend downward at middle parts thereof. Of the power side terminals and the control side terminals, only on the other ends side of the power side terminals, heat dissipation portions protruding in a direction approaching or away from the mold resin from portions bent downward are formed.

Abstract: An LED bulb with an LED assembly, including a substrate having a first top surface, longer side surface and shorter side surface; a mount disposed on the first top surface, having a first inner side surface and second inner side surface facing the first inner side surface; a plurality of LED chips on the first top surface, arranged between the first and second inner side surfaces, having a second top surface; an electrode plate formed on the mount, electrically connected to the plurality of LED chips with a third top surface which does not extend beyond the shorter side surface in a top view; and a phosphor layer covering the plurality of LED chips, mount, and electrode plate, without covering the side surfaces; and a cover covering the LED assembly. The third top surface is higher than the second top surface in an elevation based on the first top surface.

Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Abstract: Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface are disclosed. The methods may include: contacting the substrate with a plasma generated from a hydrogen containing gas, selectively forming a passivation film from vapor phase reactants on the first dielectric surface while leaving the second metallic surface free from the passivation film, and selectively depositing the target film from vapor phase reactants on the second metallic surface relative to the passivation film.

Abstract: A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.

Abstract: A component includes a carrier and a semiconductor body arranged on the carrier, wherein the semiconductor body includes a semiconductor layer facing away from the carrier, a further semiconductor layer facing the carrier and an optically active layer located therebetween, the carrier has a metallic carrier layer that is contiguous and mechanically stabilizes the component, the carrier includes a mirror layer disposed between the semiconductor body and the metallic carrier layer, the carrier has a compensating layer directly adjacent to the metallic carrier layer and is configured to compensate for internal mechanical strains in the component, and the compensating layer is arranged between the semiconductor body and the metallic carrier layer.

Abstract: The present disclosure provides a semiconductor device with an anti-fuse and a metal-insulator-metal (MIM) capacitor connected to a redistribution layer (RDL) and a method for forming the semiconductor device. The semiconductor device includes a first conductive portion and a second conductive portion disposed over a semiconductor substrate. The semiconductor device also includes a passivation layer covering the first conductive portion and the second conductive portion. The first conductive portion, the second conductive portion and a portion of the passivation layer therebetween form an anti-fuse. The semiconductor device further includes a first metal-insulator-metal (MIM) capacitor and a first redistribution layer (RDL) disposed over the passivation layer. The first MIM capacitor and the first RDL are electrically connected to the first conductive portion, and a first metal layer of the first MIM capacitor is integrally formed with the first RDL.

Abstract: A sealing member containing conductive particles and disposed in a seal region is formed between a display panel and a touch panel. A laminated structure formed on the display panel includes a first detection lines. The first detection lines extend from the seal region to a connection region and are connected through the conductive particles to terminals of second detection lines formed on the touch panel. A peripheral edge of the organic barrier is located inward from the conductive particles of the sealing member. The above described structure can facilitate a work for connecting external lines such as FPC to the display panel and the touch panel. Further, the structure can secure stability of electrical connection between the external lines and the touch panel.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that that comprises a transparent, translucent, non-opaque, or otherwise optically-transmissive, external surface.

Abstract: In some examples, an electronic device comprises a first magnetic member, a first adhesive layer abutting the first magnetic member, a second magnetic member, a second adhesive layer abutting the second magnetic member, and a laminate member between the first and second adhesive layers. The laminate member comprises first and second transformer coils, an electromagnetic interference (EMI) shield coil, and a set of thermally conductive members coupled to the EMI shield coil and extending in three dimensions. At least some of the thermally conductive members extend vertically through a thickness of the laminate member so as to be exposed to top and bottom surfaces of the laminate member. The electronic device includes a thermally conductive component coupled to at least one thermally conductive member in the set of thermally conductive members.

Abstract: A light emitting element includes a laminated structure formed by laminating a first light reflecting layer 41, a light emitting structure 20, and a second light reflecting layer 42. The light emitting structure 20 is formed by laminating, from the first light reflecting layer side, a first compound semiconductor layer 21, an active layer 23, and a second compound semiconductor layer 22. In the laminated structure 20, at least two light absorbing material layers 51 are formed in parallel to a virtual plane occupied by the active layer 23.

Abstract: Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.