Abstract: A wafer processing method includes preparing a holding table having a blade clearance portion formed therein so as to correspond to a notch of a wafer, holding the wafer by the holding table so as to make the notch of the wafer correspond to the blade clearance portion of the holding table, reducing the diameter of the wafer by cutting the wafer by a cutting blade along an outer peripheral edge of the wafer in a state in which an end of the cutting blade is positioned below the holding surface of the holding table and therefore removing at least a part of the notch portion, and forming a second notch in the wafer by cutting the wafer in a thickness direction by the cutting blade along the blade clearance portion of the holding table.

Abstract: Techniques for growing, at least one of: (a) quantum dots and (b) nano-crystals, on a surface of a material are provided. One method comprises placing a precursor on the surface; adding an antisolvent to the precursor; and growing at least one of the quantum dots and the nanocrystals on the surface.

Abstract: A semiconductor package includes a first semiconductor chip having a plurality of first through-electrodes and a plurality of first upper connection pads respectively connected to the plurality of first through-electrodes, where the plurality of first upper connection pads are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and having a plurality of second lower connection pads on a lower surface of the second semiconductor chip, and a plurality of connection members, each including a pillar and a conductive bump, the plurality of connection members electrically connecting respective ones of the first upper connection pads and the second lower connection pads to each other. Conductive bumps of adjacent connection members, among the plurality of connection members, are alternately disposed at different levels with respect to the upper surface of the first semiconductor chip.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.

Abstract: A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.

Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for fabricating a semiconductor device. A semiconductor device includes: an active device layer a local interconnect layer disposed above the active device layer; a dielectric layer disposed above the local interconnect layer; a metal layer disposed above the dielectric layer; and one or more metal sections disposed in the dielectric layer underneath one or more metal regions of the metal layer, wherein none of the one or more metal sections is electrically connected to a trace in the local interconnect layer.

Abstract: An organic light emitting display device according to an example comprises a substrate; a plurality of first bank layers disposed on the substrate in a first direction and a second direction different from the first direction to define a plurality of pixels; a plurality of second bank layers disposed on the first bank layers in the first direction to partition pixel columns of different colors; and a third bank layer formed in each of the pixel columns in the second direction to divide each of the pixel columns into a plurality of groups each including a plurality of the pixels.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.

Abstract: A semiconductor device includes a substrate, semiconductor wires disposed over the substrate, a gate structure wrapping around each of the semiconductor wires, and an epitaxial source/drain (S/D) feature in contact with the semiconductor wires. A portion of the epitaxial S/D feature is horizontally surrounded by an air gap.

Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

Abstract: The present disclosure provides methods for forming a metal containing material onto a substrate with good film uniformity and stress profile across the substrate. In one embodiment, a method of sputter depositing a metal containing layer on a substrate includes supplying a gas mixture into a processing chamber, forming a first portion of a metal containing layer on a substrate, transferring the substrate from the processing chamber, rotating the substrate, transferring the substrate back to the processing chamber, and forming a second portion of the metal containing layer on the first portion of the metal containing layer.

Abstract: A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad.

Abstract: A light emitting device includes a substrate, a buffer layer, a first active layer, and a plurality of mesa regions. A portion of the first active layer includes a first electrical polarity. The plurality of mesa regions includes at least a portion of the first active layer, a light emitting region on the portion of the first active layer, and a second active layer on the light emitting region. A portion of the second active layer includes a second electrical polarity. The light emitting region is configured to emit light which has a target wavelength between 200 nm to 300 nm. A thickness of the light emitting region is a multiple of the target wavelength, and a dimension of the light emitting region parallel to the substrate is smaller than 10 times the target wavelength, such that the emitted light is confined to fewer than 10 transverse modes.

Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

Abstract: An image generator for use in a display device, the image generator comprising a plurality of ILED array chips each comprising a plurality of ILED emitters and arranged in an array such that each of a plurality of pixels of the image generator comprises an ILED emitter from each of a plurality of adjacent ILED array chips. The total area of ILED emitter material be less than 50% of the area of each pixel. The image generator may comprise secondary optics in optical communication with an output of the plurality of ILED emitters of an ILED array chip and configured to direct light from the ILED emitters towards an emission region of the associated pixel.

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Abstract: A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.