Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

Abstract: A structure is manufactured by forming a mask that has an opening pattern on a surface of a substrate, etching the surface of the substrate with the mask to form a recessed portion corresponding to the opening pattern of the mask, forming a thin film including aluminum on a bottom surface of the recessed portion in a state where the mask remains, treating the thin film including aluminum with hot water to change the thin film into a fine recessed and projected layer including alumina hydrate smaller than the recessed portion, etching the bottom surface of the recessed portion, on which the fine recessed and projected layer is formed, in a state where the mask remains to form a fine recessed and projected structure on the bottom surface of the recessed portion, and thereafter removing the mask and the fine recessed and projected structure, which remains after the etching step.

Abstract: The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which prevents the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

Abstract: Plasma processing apparatus for processing a workpiece are provided. In one example embodiment, a plasma processing apparatus for processing a workpiece includes a processing chamber, a plasma chamber separated from the processing, and an inductively coupled plasma source configured to generate a plasma in the plasma chamber. The apparatus includes a pedestal disposed within the processing chamber configured to support a workpiece. The apparatus includes an insert disposed in the plasma chamber movable to one or more vertical positions within the plasma chamber. Methods for processing of workpieces are also provided.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.

Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes etching a substrate to form a recess within a surface of the substrate. An epitaxial material is formed within the recess, a capping structure is formed on the epitaxial material, and a capping layer is formed onto the capping structure. The capping layer laterally extends past an outermost sidewall of the capping structure. Dopants are implanted into the epitaxial material. Implanting the dopants into the epitaxial material forms a first doped region having a first doping type and a second doped region having a second doping type.

Abstract: A substrate processing method includes a first process configured to process a substrate with a top plate disposed nearer an upper surface of the substrate, the substrate being held by a substrate holding unit of a first substrate holding apparatus, a second process configured to raise the substrate with the top plate disposed on the first substrate holding apparatus to make a space between the substrate holding unit and the substrate, a third process configured to insert a substrate conveyance apparatus for conveying the substrate with the top plate disposed on the first substrate holding apparatus to a second substrate holding apparatus into the space, and a fourth process configured to convey the substrate to the second substrate holding apparatus.

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Abstract: A method for manufacturing a stacked capacitor structure includes: forming a first patterned structure over a substrate; forming a first bottom electrode over the first patterned structure; depositing a first dielectric film over the first bottom electrode; depositing a first top electrode layer over the first dielectric film; forming a first vertical interconnect structure; forming a second patterned structure over the first top electrode layer; forming a second bottom electrode over the second patterned structure and electrically connected to the first bottom electrode through the first vertical interconnect structure; depositing a second dielectric film over the second bottom electrode; depositing a second top electrode layer over the second dielectric film; and forming a second vertical interconnect structure extending from the first top electrode layer. The second top electrode layer is electrically connected to the first top electrode layer through the second vertical interconnect structure.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips.

Abstract: Embodiments of the present disclosure provide a temperature change rate control device, applied to a process chamber of a semiconductor process apparatus, including a temperature monitor unit, a controller, a gas inflation mechanism, and a gas extraction mechanism. The temperature monitor unit is configured to obtain a temperature of a wafer in the process chamber in real time. The controller is configured to calculate a temperature change rate of the wafer according to the temperature obtained by the temperature monitor unit. The gas inflation mechanism communicates with the process chamber. The gas extraction mechanism communicates with the process chamber. When the temperature change rate is outside a predetermined temperature change rate range, a first control signal is sent to the gas inflation mechanism, and/or a second control signal is sent to the gas extraction mechanism to control the temperature change rate within the temperature change rate range.

Abstract: The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Abstract: Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may define one or more recessed features. The methods may include providing a second precursor to the processing region. The methods may include forming a plasma of the carbon-containing precursor and the second precursor in the processing region. Forming the plasma of the carbon-containing precursor and the second precursor may be performed at a plasma power of greater than or about 500 W. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more recessed features. The methods may include, subsequent depositing the carbon-containing material for a first period of time, applying a bias power while depositing the carbon-containing material for a second period of time.

Abstract: A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.

Abstract: A process for producing a receiver substrate for a semiconductor-on-insulator structure for radiofrequency application comprises the following steps:—providing a semiconductor substrate comprising a base substrate made of monocrystalline material and a charge-trapping layer made of polycrystalline silicon arranged on the base substrate;—oxidizing the charge-trapping layer to form an oxide layer arranged on the charge-trapping layer. The oxidation of the charge-trapping layer is performed at least partly at a temperature lower than or equal to 875° C., in the following manner:—starting the oxidization at a first temperature (T1) between 750° C. and 1000° C.;—decreasing the temperature down to a second temperature (T2), lower than the first temperature (T1), between 750° C. and 875° C.;—continuing the oxidization at the second temperature (T2).

Abstract: A method for bonding a first substrate and a second substrate comprises bringing the first and second substrates into contact and implementing heating of a peripheral zone of at least one of the first and second substrates. The heating is initiated before the substrates are brought into contact and continued at least until the substrates are brought into contact in the zone. The heating is implemented by an infrared lamp configured to emit radiation having an outer boundary corresponding to the edge of the substrates.

Abstract: There is provided a technique that includes: organically terminating a first region of a substrate by supplying an adsorption control agent containing an organic ligand to the substrate while regulating a temperature of the substrate including the first region and a second region different from the first region formed on a surface of the substrate depending on a composition of the first region; and selectively growing a film on the second region by supplying a deposition gas to the substrate.