Patents Examined by Quovaunda Jefferson
  • Patent number: 11315786
    Abstract: The present disclosure provides a semiconductor device structure with fine patterns at different levels and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns and reduces the parasitic capacitance between fine patterns The semiconductor device structure includes a substrate; a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; a second target structure disposed over the target layer, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion: a low-level conductive pattern positioned between the first target structure and the second target structure; and a high-level conductive pattern positioned in the first target structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Patent number: 11316043
    Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
  • Patent number: 11309429
    Abstract: A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joonseok Park, Jihun Lim, Myounghwa Kim, Taesang Kim, Yeonkeon Moon
  • Patent number: 11295958
    Abstract: Methods of forming a semiconductor device and semiconductor device formed by the methods are provided. The methods of forming a semiconductor device may include providing a first substrate and a first bonding layer that is provided on the first substrate, forming a sacrificial pattern and an active pattern on a second substrate, forming a second bonding layer on the active pattern, bonding the second bonding layer onto the first bonding layer, removing the second substrate, and removing the sacrificial pattern to expose the active pattern. Forming the sacrificial pattern and the active pattern on the second substrate may include forming a preliminary sacrificial pattern and the active pattern on the second substrate and oxidizing the preliminary sacrificial pattern. The preliminary sacrificial pattern and the active pattern may be sequentially stacked on the second substrate.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 5, 2022
    Inventors: Sungmin Kim, Daewon Ha
  • Patent number: 11251389
    Abstract: A quantum dot, a quantum dot light emitting diode and a quantum dot display device are discussed. The quantum dot includes a first core including a first semiconductor material, a first shell positioned at an outer side of the first core and including a second semiconductor material, and a second core positioned between the first core and the first shell and including one of the first and second semiconductor materials and a doping metal.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 15, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kyu-Nam Kim, Hye-Li Min, Min-Surk Hyung
  • Patent number: 11232989
    Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Chun Chang, Guan-Jie Shen
  • Patent number: 11222868
    Abstract: Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Ed A. Schrock
  • Patent number: 11217597
    Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ching-Wen Chan
  • Patent number: 11211569
    Abstract: Organic semiconductor compositions (OSCs) compatible with laser printing techniques are described herein. In being compatible with laser printing techniques, the OSCs are in particulate form and generally comprise an organic semiconductor component and carrier. The organic semiconductor component can comprise any small molecule semiconductor or polymeric semiconductor not inconsistent with the laser printing methods.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: December 28, 2021
    Assignee: WAKE FOREST UNIVERSITY
    Inventors: Oana Diana Jurchescu, Peter James Diemer
  • Patent number: 11183495
    Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 23, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sun-hak Lee, Yong Zhong Hu, Hye-mi Kim
  • Patent number: 11177169
    Abstract: A method of fabricating a semiconductor device includes depositing a spacer material in a trench arranged in a dielectric layer. An end of the trench extends to a metal layer of an interconnect structure. A portion of the spacer material in contact with the metal layer is removed. A recess is formed in the metal layer at the end of the trench.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang, Hosadurga Shobha
  • Patent number: 11152494
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 11121073
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Travis Lajoie, Abhishek Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh, Allen Gardiner, Blake Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
  • Patent number: 11114407
    Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
  • Patent number: 11101133
    Abstract: An object of the present invention is to provide stable withstand voltage characteristics, reduce turn-off losses along with a reduction in leakage current when the device is off, improve controllability of turn-off operations, and improve blocking capability at turn-off. An N buffer layer includes a first buffer layer joined to an active layer and having one peak in impurity concentration, and a second buffer layer joined to the first buffer layer and an N? drift layer, having at least one peak point in impurity concentration, and having a lower maximum impurity concentration than the first buffer layer. The impurity concentration at the peak point of the first buffer layer is higher than the impurity concentration of the N? drift layer, and the impurity concentration of the second buffer layer is higher than the impurity concentration of the N? drift layer in the entire area of the second buffer layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 24, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 11092862
    Abstract: An electro-optical device includes a pixel electrode that is light-transmissive, a substrate that is light-transmissive and that is provided with a recessed portion open to the pixel electrode side, a light-shielding body disposed in the recessed portion, and a switching element overlapping, in a plan view from a thickness direction of the substrate, the light-shielding body, the switching element being electrically coupled to the pixel electrode, wherein the light-shielding body includes a metal film containing tungsten, and a metal nitride film that is disposed between the metal film and the substrate and that contains tungsten nitride.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 17, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11088264
    Abstract: In one example, a field effect transistor includes a fin. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator. A gate is wrapped around the conducting channel, between the source/drain regions. In another example, a method for fabricating a field effect transistor includes forming a fin on a wafer. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator. A gate is also formed between the source/drain regions and wraps around the conducting channel.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 11088115
    Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONIC CO., LTD.
    Inventors: Jungsoo Byun, Taesung Jeong, Younggwan Ko, Jaeean Lee
  • Patent number: 11069868
    Abstract: The present invention relates to a semiconductor structure. The semiconductor structure comprises a semiconductor layer, at least one metallic carbon nanotube, and at least one graphene layer. The semiconductor layer defines a first surface and a second surface opposite to the first surface. The at least one metallic carbon nanotube is located on the first surface of the semiconductor layer. The at least one graphene layer is located on the second surface of the semiconductor layer. The at least one metallic carbon nanotube, the semiconductor layer and the at least one graphene layer are stacked with each other to form at least one three-layered stereoscopic structure. The present invention also relates a semiconductor device, and a photodetector.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 20, 2021
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke Zhang, Yang Wei, Shou-Shan Fan
  • Patent number: 11062901
    Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia Cheng Chou, Po-Cheng Shih, Li Chun Te, Tien-I Bao