Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.

Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the silicon-containing precursor and the boron-containing precursor. The dopant-containing precursor may include one or more of carbon, nitrogen, oxygen, or sulfur. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The silicon-and-boron material may include greater than or about 1 at. % of a dopant from the dopant-containing precursor.

Abstract: A method and system for connecting electronic assemblies and/or for manufacturing workpieces, having a plurality of modules for connecting the electronic assemblies, includes at least one module configured as a loading station and/or unloading station. At least one further module is configured as a manufacturing station. A manufacturing workpiece carrier is provided for accommodating the electronic assemblies and/or the workpieces, and is movable in automated manner by way of a conveying unit from the loading station via the manufacturing station to the unloading station. The system is configured in particular for assembly line production. In a secondary aspect, a foil/film transfer unit is proposed which provides automated application of foils/films as a process cover in the loading station.

Abstract: A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body.

Abstract: A protective sheeting for use in processing a semiconductor-sized wafer includes a protective film and a cushioning layer attached to a back surface of the protective film. At least in a central area of the protective sheeting, no adhesive is applied to a front surface and a back surface of the protective sheeting, the central area having an outer diameter which is equal to or larger than an outer diameter of the semiconductor-sized wafer. Further, a protective sheeting for use in processing a wafer has a protective film and a cushioning layer attached to a back surface of the protective film, wherein, on an entire front surface and an entire back surface of the protective sheeting, no adhesive is applied. A handling system for a semiconductor-sized wafer and to a combination of a wafer and the protective sheeting are also described.

Abstract: Methods of forming indium gallium zinc oxide (IGZO) films by vapor deposition are provided. The IGZO films may, for example, serve as a channel layer in a transistor device. In some embodiments atomic layer deposition processes for depositing IGZO films comprise an IGZO deposition cycle comprising alternately and sequentially contacting a substrate in a reaction space with a vapor phase indium precursor, a vapor phase gallium precursor, a vapor phase zinc precursor and an oxygen reactant. In some embodiments the ALD deposition cycle additionally comprises contacting the substrate with an additional reactant comprising one or more of NH3, N2O, NO2 and H2O2.

Abstract: A metal organic chemical vapor deposition system includes a reaction chamber, a first heater arranged on a first side of the reaction chamber, and a second heater arranged on a second side of the reaction chamber. A controller is configured to selectively control an amount of heat applied by the second heater to the reaction chamber depending on a type of vapor deposition being performed in the reaction chamber.

Abstract: A method of forming a device structure including a selectively-deposited gallium nitride layer is disclosed.

Abstract: Embodiments include a microelectronic package structure having a substrate with one or more substrate pads on a first side of the package substrate. A ball interconnect structure is on the substrate pad, the ball interconnect structure comprising at least 99.0 percent gold. A discrete component having two or more component terminals is on the ball interconnect structure.

Abstract: A thin film formation apparatus includes a chamber, a platen disposed within the chamber, a heater configured to heat the platen within the chamber, a gas inlet communicating with an interior of the chamber and configured to supply a reducing gas and inert gas to the interior of the chamber, a target disposed within the chamber and spatially separated from the platen, and a microwave plasma source disposed adjacent to the target. The reducing gas includes at least one of hydrogen (H2) and deuterium (D2).

Abstract: This disclosure relates to a multilayer structure containing: a substrate; a coupling layer deposited on the substrate; and a dielectric layer deposited on the coupling layer, wherein shear strength is increased by a factor of at least about 2 in the presence of the coupling layer compared to a multilayer in the absence of the coupling layer.

Abstract: The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

Abstract: A method includes forming a resist pattern, the resist pattern having trenches oriented lengthwise along a first direction and separated by resist walls along both the first direction and a second direction perpendicular to the first direction. The method further includes loading the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction, and tilting the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method further includes rotating the resist pattern around the axis to a first position; implanting ions into the resist walls with the resist pattern at the first position; rotating the resist pattern around the axis by 180 degrees to a second position; and implanting ions into the resist walls with the resist pattern at the second position.

Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.

Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Abstract: A light-emitting diode (LED) chip (2) comprises a substrate (20), an epitaxial structure (21), a transparent conductive layer (22), a passivation protective layer (23), and at least one electrode (25). The epitaxial structure (21) is disposed on the substrate (20). The transparent conductive layer (22) is disposed on the epitaxial structure (21). The transparent conductive layer (22) defines one or more first through holes (220) that extend through the transparent conductive layer (22). The passivation protective layer (23) is disposed on the transparent conductive layer (22). The passivation protective layer (23) defines one or more second through holes (230) that extend through the passivation protective layer (23). The electrode (25) is disposed on the passivation protective layer (23). The electrode (25) electrically connects the transparent conductive layer (11) through the one or more second through holes (230).

Abstract: A semiconductor device includes a first dielectric layer over a device base layer, the first dielectric layer having a first opening with a first sidewall; a first interconnect segment extending through the first opening; and a cap layer over a top surface of the first interconnect segment, wherein the cap layer comprises a first metal, carbon, and nitrogen.

Abstract: A production method for a semi-conductor-on-insulator type multilayer stack includes ion implantation in a buried portion of a superficial layer of a support substrate, so as to form a layer enriched with at least one gas, intended to form a porous semi-conductive material layer, the thermal oxidation of a superficial portion of the superficial layer to form an oxide layer extending from the surface of the support substrate, the oxidation and the implantation of ions being arranged such that the oxide layer and the enriched layer are juxtaposed, and the assembly of the support substrate and of a donor substrate.