Patents Examined by Raymond Phan
  • Patent number: 10146712
    Abstract: A method of communicating with a peripheral device in a host operating system (OS) and a guest OS installed on an electronic device includes: receiving, by the host OS, first data from the guest OS; determining, by the host OS, whether to switch from a first communication link to a second communication link to transmit and receive data between the electronic device and the peripheral device; packetizing, by the host OS, the first data based on the determination; and transmitting the packetized data to the peripheral device.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bok-deuk Jeong, Anatoly Stepanov, Sung-min Lee
  • Patent number: 10146585
    Abstract: Ensuring the fair utilization of system resources using workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queuing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and responsive to detecting that additional system resources in the storage system have become available, issuing an I/O request from an entity-specific queue for an entity that has a highest priority among entities with non-empty entity-specific queues.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 4, 2018
    Assignee: Pure Storage, Inc.
    Inventors: Yuval Frandzel, Kiron Vijayasankar
  • Patent number: 10146715
    Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
  • Patent number: 10127012
    Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: John Howard, Steven B. McGowan, Krzysztof Perycz
  • Patent number: 10114781
    Abstract: Methods, structures, and apparatus that limit the amount of dendritic growth and metal migration between contacts in order to prevent an erroneous detection of a connection and/or functional failure. One example may reduce dendritic growth and metal migration by limiting an amount of time that a connection detection voltage is applied to CC contacts of a USB Type-C connector when an electronic device is detecting a connection. This and other examples may further limit dendritic growth by not applying the connection detection voltage to the CC contacts for a first duration following a detection of a disconnection.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 30, 2018
    Assignee: Apple Inc.
    Inventors: Colin Whitby-Strevens, Kevin M. Keeler, Christophe B. Daniel
  • Patent number: 10108377
    Abstract: The embodiments disclosed herein include an interconnection network that is configured to provide data communication between storage processing units. The disclosed interconnection network can be particularly effective when the storage processing units are configured to locally perform scientific computations. The disclosed interconnection network can enable localized, high throughput, and low latency data communication between storage processing units without overloading the host system.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 23, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Arup De, Kiran Kumar Gunnam
  • Patent number: 10108431
    Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 23, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean, Stephan Gaskins
  • Patent number: 10089251
    Abstract: A system and method for providing a multi-modal active cable. In certain embodiments, the multi-modal active cable enables transmission of alternative display information from a source system. More specifically, in certain embodiments, the multi-modal active cable comprises a switching component to allow host system integrated I/O signals to be provided as either I/O adapter integrated I/O signals or dedicated display signals via a single multi-modal active cable. In certain embodiments, the integrated I/O signals comprise Thunderbolt I/O signals. In certain embodiments, the dedicated display signals comprise DisplayPort signals. In certain embodiments the switching component comprises at least one radio frequency (RF) microwave high performance analog switches to switch the high speed digital signals (e.g., signal speeds up to 40 Gbps on each of a plurality of lane). By using such switches, the load capacitance on the signal paths is minimized as the impedance is carefully controlled.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 2, 2018
    Assignee: Dell Products L.P.
    Inventors: Thomas E. Voor, Sean P. O'Neal
  • Patent number: 10088514
    Abstract: Techniques described herein include a method, system, and apparatus for detecting an orientation configuration. For example, an apparatus having an all-in-one port may include a first configuration pin and a second configuration pin. The apparatus may also include logic configured to enter into an accessory mode based on a presence of a first signal on the first configuration pin and a second signal on the second configuration pin. The logic may be further configured to provide an orientation indication by altering the first signal on the first configuration pin.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Rolf Kuehnis, Robert A. Dunstan
  • Patent number: 10089232
    Abstract: Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a portion of allocated pins of a processor with switchable pins, connecting the processor to a memory interface configured to switch the switchable pins between a power mode and a signal mode, providing a metric configured to identify which of the power mode and the signal mode is most beneficial during 1 millisecond intervals, and switching the switchable pins to signal mode during intervals where the signal mode provides more benefit than the power mode.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: October 2, 2018
    Assignee: Board of Supervisors of Louisiana State University and Agricultural and Mechanical College
    Inventors: Lu Peng, Ashok Srivastava, Shaoming Chen
  • Patent number: 10089157
    Abstract: An Autonomous Concurrency Management (ACM) subsystem enables test instruments (operating as servers) to reliably and efficiently handle a variety of seamless multi-device-under-test (multi-DUT) scenarios and with minimal cooperation from the original equipment manufacturer (OEM) client software (e.g. test plans, hardware abstraction layer, etc.). Concurrency capability is built directly into the test instruments. Making the instrument based concurrency autonomous means the OEM software code base need not be specifically implemented for concurrency, potentially saving thousands of lines of OEM software code. To support basic concurrency scenarios where clients asynchronously share the instrument, as well as advanced concurrency scenarios such as a broadcast scenario, the ACM includes software lock, client separator, client rendezvous, and client observer functionality.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 2, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Mark R. DeWitt
  • Patent number: 10083134
    Abstract: Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.
    Type: Grant
    Filed: November 28, 2015
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind
  • Patent number: 10078606
    Abstract: A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 18, 2018
    Assignee: KnuEdge, Inc.
    Inventors: Douglas A. Palmer, Jerome Vincent Coffin, Andrew Jonathan White, Ramon Zuniga
  • Patent number: 10078601
    Abstract: In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: September 18, 2018
    Assignee: Cavium, Inc.
    Inventors: Wilson P. Snyder, II, Anna Kujtkowski, Albert Ma, Paul G. Scrobohaci
  • Patent number: 10049073
    Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 14, 2018
    Assignee: Apple Inc.
    Inventors: Michael J. Smith, Josh P. de Cesare, Brijesh Tripathi, Derek Iwamoto, Shane J Keil
  • Patent number: 10049059
    Abstract: In one aspect, a first device includes a housing, at least one system component housed by the housing, a connector coupled to the housing that engages with a second device for exchange, between the first device and the second device, of at least one of data and power, and a first magnet coupled to the housing. The first magnet is coupled to the housing so that a first pole of the first magnet faces away from the first device to repel a first pole of a second magnet coupled to the second device when the first device is juxtaposed next to the second device in a first orientation relative to the second device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 14, 2018
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Peter Carlson Rane, Ali Kathryn Ent, Thomas Perelli, Vincent Charles Conzola
  • Patent number: 10037067
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • Patent number: 10037295
    Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: July 31, 2018
    Assignee: The Regents of the University of Michigan
    Inventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
  • Patent number: 10031857
    Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 24, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Menachem, Shlomo Raikin, Idan Burstein, Michael Kagan
  • Patent number: 10025745
    Abstract: A computer system and a method are provided for accessing a peripheral component interconnect express (PCIe) endpoint device. The computer system includes: a processor, a PCIe bus, and an access proxy. The access proxy connects to the processor and the PCIe endpoint device; the processor acquires an operation instruction, where the operation instruction instructs the processor to access the PCIe endpoint device through the access proxy, and send an access request to the access proxy according to the operation instruction; and the access proxy sends a response message of the access request to the processor after receiving the access request sent by the processor. Because the processor does not directly access the PCIe endpoint device to be accessed but completes access through the access proxy, thereby avoiding an MCE reset for the processor.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 17, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Ge Du