Abstract: An electronics adapter, system, and methods for using multiple interface ports to execute a single function are disclosed herein. The electronics adapter may include multiple interface ports, each having a transmission capacity for data transmitted via each interface port. Processing logic may be coupled to the two or more interface ports, to execute processes associated with the multiple interface ports utilizing a bandwidth. The electronics adapter may further include a controller to configure and merge the data from the multiple interface ports based at least in part on the transmission capacities for the multiple interface ports to support the bandwidth of the processes.

Abstract: A technique for handling interrupts in a data processing system includes maintaining, at an interrupt presentation controller (IPC), an interrupt acknowledge count (IAC). The IAC provides an indication of a number of times a virtual processor thread implemented at a first software stack level has been interrupted in response to receipt of event notification messages (ENMs) from an interrupt source controller (ISC). In response to the IAC reaching a threshold level, the IPC transmits an escalate message to the ISC. The escalate message includes an escalate event number that is used by the ISC to generate a new ENM that targets a second software stack level that is different than the first software stack level and is associated with another virtual processor thread.

Abstract: An electronics adapter and method are disclosed herein. The electronics adapter can include a plurality of interface ports, with each interface port from the device coupled to a processor from a plurality of processors, and a controller communicatively coupled to the interface ports. The controller may be configured to determine a function or transaction attributes, which are serviced by instructions executed by one of the processors. The controller may be further configured to determine at least one interface port on the adapter to transmit the transaction based on the function or the attributes using an updatable mapping between the function or the attributes and the interface port, and transmit a request for the transaction using the interface port for processing of the transaction by the processor coupled to the interface port.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: Described systems and methods allow conducting computer security operations, such as detecting malware and spyware, in a bare-metal computer system. In some embodiments, a first processor of a computer system executes the code samples under assessment, whereas a second, distinct processor is used to carry out the assessment and to control various hardware components involved in the assessment. Such hardware components include, among others, a memory shadower configured to detect changes to a memory connected to the first processor, and a storage shadower configured to detect an attempt to write to a non-volatile storage device of the computer system. The memory shadower and storage shadower may be used to inject a security agent into the computer system.

Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.

Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.

Abstract: A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.

Abstract: An information handling system (IHS) server volume includes at least two pairs of flexible peripheral component interconnect express (PCIe) media for connecting data signals and power supply signals via riser cards mounted against respective PCIe devices in large adjacent physical slot locations. A first PCIe device corresponding to a first riser card and a second PCIe device corresponding to a second riser card are relatively positioned to enable the second riser card to be fitted within a specified space between the first PCIe device and the first riser card while a footprint of a first PCIe connector corresponding to the first PCIe device overlaps a footprint of a second PCIe connector corresponding to the second PCIe device. First and second PCIe cards provided by the first and second PCIe devices respectively are inserted into respective PCIe connectors via the first pair of riser cards having a dense nested arrangement.

Abstract: A peripheral component interconnect express (PCIe) eXtensions for instrumentation (PXIe) chassis includes a backplane, multiple peripheral slots, a mezzanine card and an integrated accelerator module. The peripheral slots are located on the backplane and configured to receive insertable PXIe peripheral modules, respectively. The mezzanine card is on the backplane and configured to accommodate at least one of connectors, integrated circuits (ICs) and signal lines incorporated in the PXIe chassis. The integrated accelerator module is on the mezzanine card within the PXIe chassis and configured to accelerate processing of signals received from the PXIe peripheral modules.

Abstract: A coprocessor (PL) is disclosed. The PL includes a memory router, at least one collection block that is configured to transfer data to/from the memory router, each collection block includes a collection router that is configured to i) transfer data to/from the memory router, ii) transfer data to/from at least one collection router of a neighboring collection block, and iii) transfer data to/from blocks within the collection block, and at least one programmable operator that is configured to i) transfer data to/from the collection router, and ii) perform a programmable operation on data received from the collection router.

Abstract: An information handling system port selectively communicates differential and single-ended signals from port pins to a cable coupled with the port so that bandwidth of information sent through the port increases if a cable accepts single-ended signals. Single-ended signals sent from the port pins are provided to a redriver of the cable to generate differential signals on wireline pairs of the cable. The redriven single-ended signals effectively double the bandwidth from reconfigured differential pairs of a port without increasing the port footprint or altering the port from a standard form factor, such as a Type-C USB form factor.

Abstract: Systems, methods, circuits, devices and computer-readable mediums for configuring serial devices are disclosed. In some implementations, a device comprises: an input for receiving first and second requests from a serial bus; a decoder coupled to the input and configured to determine if either of the first and second requests is a configuration mode request; a controller coupled to the decoder and configured to: in response to a determination that the first request is a configuration mode request, program a configuration block with configuration data obtained from the serial bus and alter a device behavior according to the configuration data; and in response to a determination that the second request is not a configuration mode request, perform one or more actions on the device according to the second request.

Abstract: Embodiments herein provide for tag allocation in a PCIe application layer. In one embodiment, an apparatus operable to interface with a plurality of virtual functions and a plurality of physical functions to process data via the PCIe protocol. The apparatus includes a packet builder communicatively coupled to each of the virtual functions and the physical functions and operable to build packets for non-posted commands from the virtual and physical functions. The apparatus also includes a tag allocator operable to allocate tags from a first set of tags to the packets of non-posted commands from any of the virtual and physical functions employing extended tags when the tags of the first set are available, and to reserve a second different set of tags for remaining virtual and physical functions not employing extended tags until the first set of tags are all allocated.

Abstract: A computer apparatus, a datapath switching method and an associated method are provided. An operating system utilized by the computer apparatus is detected by an embedded controller, and datapaths for transmitting sensing signals to a platform controller hub are switched according to the operating system utilized by the computer apparatus by the embedded controller.

Abstract: A wireless network system can be provided with a one-way communication link for communicating a beacon signal between beacon circuitries of two electronic devices. According to information stored in the beacon signal, the device that receives the beacon signal can activate a primary communication circuitry to enable communication of primary communication data signals with a primary communication circuitry of the device that transmitted the beacon signal. The beacon circuitries of the two devices may require less power than the primary communication circuitries of the two devices.

Abstract: A method and apparatus for setting an internal register of an integrated circuit (IC) via a multiplexed pin which also passes an RF signal is provided. An internal RF signal path couples the pin to an internal terminal for the RF signal, and a register setting signal path couples the pin to an internal register. The internal register may be an address register, such as a USID address register of a MIPI RFFE bus. A capacitor on the RF signal path may block the constant voltage, and a resistor or inductor on the register setting signal path may block the RF signal. The integrated circuit may include an RF section and a controller section, where the controller section may be used to control the RF section. The controller section is responsive to an address associated with the address register.

Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a command signal and creates data transmission link to the computer device. The master storage unit has at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to transmit the command signal from the master storage unit to the slave storage unit.

Abstract: A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device.

Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.