Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.

Abstract: Provided are systems, methods, and computer-program products for enabling peer-to-peer communications between peripheral devices in a computing system. In various implementations, a host device in the computing system can read an address from a peripheral device included in the computing system. The host device can further configure an emulated peripheral device corresponding to the peripheral device, including writing the address to an emulated register of the emulated peripheral device. The host device can further initiate a virtual machine, including reading the address from the emulated register, initializing a page table for the virtual machine, and initiating a guest operating system. The guest operating system can be operable to use the address to access the physical device.

Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.

Abstract: Systems and methods are disclosed for configuring multi-line serial computer expansion bus communication links. A controller for a data storage device may receive one or more signals indicative of bifurcation settings from a configuration component or a host bus adapter may provide one or more signals indicative of bifurcation settings to the controller. The controller may receive configuration data from the BIOS based on the one or more signals and may configure the multi-line serial computer expansion bus communication links based on the configuration data.

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: A data stream processing unit (DPU) and methods for its use and programming are disclosed. A DPU includes a number of processing elements (PEs) arranged in a physical sequence. Each datum in the data stream visits each PE in sequence. Each PE has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. Each computing circuit implements a finite state machine that operates on the data and metadata inputs as a function of its position in the sequence and a data context, producing an altered partial computational state that accompanies the datum. When the data context changes, the current state of the finite state machine is stored, and a new state is loaded. The processing elements may be collectively programmed to perform any desired computation.

Abstract: Provided is a parallel computing system that has scalability and is capable of performing data transfer between desired PEs. Also provided is a computer system that utilizes the parallel computing system described above, and enables radiosity processing on small-scale mobile terminal devices. An HXNet is implemented in a VLSI, and data transfer between VLSIs is possible using additional BMs. Scalability is realized that enables selection of any number of VLSIs, and radiosity processing is enabled on small-scale mobile terminal devices.

Abstract: A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

Abstract: Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus. In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a high-speed parallel bit stream and then serializes the converted high-speed parallel bit stream based on a high-speed reference frequency. In another aspect, a data receiving circuit recovers the low-speed parallel bit stream from the high-speed parallel bit stream if the low-speed parallel bit stream is determined to exist in the high-speed parallel bit stream.

Abstract: A vehicle computing system comprising a vehicle auxiliary port and at least one controller. The controller configured to communicate with a nomadic device via a wired connection established between the vehicle auxiliary port and a nomadic device auxiliary port. The controller further configured to transmit data to the nomadic device over the wired auxiliary port connection. The data including one or more control commands for the nomadic device.

Abstract: A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

Abstract: A system for the management of rack-mounted field replaceable units (FRUs) that affords the enhanced availability and serviceability of FRUs provided by blade-based systems but in a manner that accommodates different types of FRUs (e.g., in relation to form factors, functionality, power and cooling requirements, and/or the like) installed within a rack or cabinet.

Abstract: Embodiments generally relate to hot-plug technology. The present technology discloses hardware and software specifications that can enable hot-plug functions for high-bandwidth and low-latency data transmission within a computing system. The present technology can provide hot-plug functions to PICe devices within a server rack by utilizing various controllers and power indicators embedded in the system. In addition to PCIe, the present technology can provide hot-plug functions to other high-throughput computer I/O (Input/Output) expansion technologies.

Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

Abstract: Embodiments are described for systems and methods of reconfiguring logical units (LUN) in a network of SCSI target endpoints by defining a first bitmap associated with each LUN of a plurality of LUNs in the network, wherein each bit of the first bitmap represents an endpoint utilizing a corresponding LUN so that a bit pattern of the first bitmap represents a first set of endpoints utilizing the corresponding LUN, applying a lock to block I/O operations to the plurality of LUNs, updating the first bitmap to generate a second bitmap representing a second set of endpoints utilizing the corresponding LUN, and releasing the lock to update a LUN to endpoint mapping for the plurality of LUNS and the endpoints in a single update operation.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

Abstract: Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.