Patents Examined by Reba I. Elmore
  • Patent number: 10042752
    Abstract: In one example in accordance with the present disclosure, a method may include identifying, by a first operating system process in a computer system accessing a shared memory heap, a first object at a first memory address in the shared memory heap. The first object may have been previously allocated in the shared memory heap by a second operating system process. The method may also include identifying an object descriptor associated with the first object at a second memory address in the shared memory heap. The object descriptor occupies a number of bits of memory independent of the type. The method may also include determining a size of the first object based on the object descriptor, enumerating, based on the object descriptor, fields associated with the first object and performing an action based on each field of the enumerated fields.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 7, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Evan R. Kirshenbaum, Lokesh Gidra
  • Patent number: 10042560
    Abstract: According to a write data request processing method and a storage array provided in the embodiments of the present invention, a controller is connected to a cache device via a switching device, an input/output manager is connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: August 7, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei Zhang, Xianhong Lu, Mingchang Wei, Chenyi Zhang
  • Patent number: 10042766
    Abstract: A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 7, 2018
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Klas Magnus Bruce, Phanindra Kumar Mannava
  • Patent number: 10037145
    Abstract: A present disclosure provides a garbage collector capable of freeing memory reachable only by a terminated thread immediately upon thread exit without scanning the heap or blocking other threads. A heap, including a plurality of spans, is walked, for example when the heap reaches a predetermined size. Reachable objects are marked in a mark bitmap. A mutator sweeps the mark bitmap without clearing mark bits, and newly allocated objects are not marked. When the thread terminates, sweep pointers in each of the spans owned by the terminated thread are reset. Moreover, a write barrier that makes a first unpublished object reachable from a second published object, also publishes the first object and all objects reachable from the first object.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 31, 2018
    Assignee: Google LLC
    Inventors: Richard Lewis Hudson, Russell Stensby Cox, David Read Chase, Austin Thomas Kona Clements
  • Patent number: 10033810
    Abstract: Embodiments for an approach to resource optimization during consistency group formation associated with a global mirror environment is provided. The approach detects when a primary volume associated with the consistency group has completed transmitting its out-of-sync (OOS) data towards its associated secondary volume. A command is sent to create a next consistency group sidefile so further writes can be sent to the sidefile rather than queueing at the primary volume. The approach repeats this process for each primary volume associated with the global mirror environment until all primary volumes are complete. Commands are sent to disable writes to the associated sidefiles and to merge the data stored in the sidefiles into normal cache as the next consistency group becomes the current consistency group.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Paul A. Jennas, II, Jason L. Peipelman, Matthew J. Ward
  • Patent number: 10015254
    Abstract: Traditionally, wireless device, such as cell phone or personal data assistant device (PDA), has relatively smaller storage capacity. Therefore, it is quite often that a user of the wireless device has difficulty to find more storage space for storing ever increased personal data, such as storing message, and multiple Gig bytes of multimedia data including digital video, music, or photo picture etc. Instant application disclosed a system and method for a storage system providing storage service to the wireless device for the wireless device remotely storing personal data into an external storage space allocated exclusively to a user of the wireless device by the storage system.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 3, 2018
    Inventor: Sheng Tai (Ted) Tsao
  • Patent number: 10007465
    Abstract: Methods of operating a memory device, and memory devices and systems so configured, include receiving a first address range for programming user data to a first range of physical memory addresses of a memory device, receiving a second address range for programming associated metadata to a second range of physical memory addresses of the memory device, determining whether the first address range is contiguous with the second address range, maintaining the second range of physical memory addresses for programming the metadata when it is determined that the second address range is contiguous with the first address range, and, when it is determined that the second address range is not contiguous with the first address range, remapping the second address range to a third range of physical memory addresses of the memory contiguous with the first range of physical memory addresses for programming the metadata.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Lance Dover, Jim Cooke, Peter Feeley
  • Patent number: 10001922
    Abstract: A data storage structure, comprising: a plurality of storage units, each comprising: a storage media; and a library executive configured to manage the storage media. The structure further comprises a buffer connected to a controller, the controller comprising: a host interface configured to receive the instruction from the host machine; an object aggregator configured to combine the plurality of data objects into a data segment; a persistent write buffer configured to store the data segment; a persistent map configured to identify a location of each of the plurality of objects in the data segment; an erasure coder configured to encode the data segment into an erasure code; a destager configured to transfer the data segment from the persistent write buffer to the storage media in a given storage unit; and a library controller configured to communicate with the library executive in the given storage unit.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Steven R. Hetzler, Wayne C. Hineman, Robert M. Rees
  • Patent number: 9990315
    Abstract: A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: June 5, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mark Moshayedi, Seyed Jalal Sadr
  • Patent number: 9977738
    Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: May 22, 2018
    Assignee: VMware, Inc.
    Inventors: Rajesh Venkatasubramanian, Puneet Zaroo, Alexandre Milouchev
  • Patent number: 9977731
    Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 22, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Hong Beom Pyeon, Jin-Ki Kim, Peter B. Gillingham
  • Patent number: 9977621
    Abstract: The present disclosure discloses a multimedia data backup method, a user terminal and a synchronizer. The method includes: triggering a first user operation, which is used for acquiring configuration data; displaying the configuration data in the display area in response to the first user operation, and selecting a backup mode from the configuration data; triggering a second user operation, which is used for executing data backup processing corresponding to the backup mode; and searching multimedia data corresponding to the backup mode in response to the second user operation, and backing up the multimedia data to the storage medium when it is detected that an amount of free storage space of the storage medium is matched with an amount of the searched multimedia data.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 22, 2018
    Assignee: ZTE CORPORATION
    Inventor: Yu Gao
  • Patent number: 9971688
    Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Karthikeyan Karthik Vaithianathan, Yoav Zach, Boris Ginzburg, Ronny Ronen
  • Patent number: 9965184
    Abstract: In one aspect, a storage management system of a storage controller having a set of processor nodes, in response to a request by a user to add a storage pool to the storage system, adds a set of subpools of storage, one for each processor node of the storage controller. The resultant storage capacity is the combination of the individual storage capacities of each subpool of the set of storage subpools. Accordingly, each subpool of the set is automatically assigned to a different processor node. In this manner, the user may be relieved of the task of manually assigning storage pools to processor nodes. In addition, load balancing between the processor nodes may be facilitated. Other aspects and features are described herein.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua J. Crawford, Paul A. Jennas, II, Jason L. Peipelman, Matthew J. Ward
  • Patent number: 9965198
    Abstract: Systems and methods for internally preconditioning SSDs for various workloads are disclosed. One such method involves (1) receiving preconditioning parameters including an invalidity distribution across ribbons, a transfer size of workloads, and a randomness of workloads, (2) generating workload data including a percentage of random data and a percentage of non-random data, where the percentages are based on the randomness of workloads parameter, (3) determining preselected physical block addresses (PBAs) of a ribbon using the invalidity distribution parameter, (4) writing a portion of the workload data to each of the preselected PBAs of the ribbon using a preselected transfer size until the ribbon is full, where the transfer size is based on the transfer size of workloads parameter, (5) marking all PBAs of the ribbon that were not preselected using the invalidity distribution parameter as being invalid, and (6) repeating (2) to (5) until a preselected end condition is met.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 8, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Timothy Glen Hallett, Anton John Neu, Phillip Peterson
  • Patent number: 9965211
    Abstract: Provided are a method, a non-transitory computer-readable storage device and an apparatus for managing use of a shared memory buffer that is partitioned into multiple banks and that stores incoming data received at multiple inputs in accordance with a multi-slice architecture. A particular bank is allocated to a corresponding slice. Received respective data packets are associated with corresponding slices based on which respective inputs they are received. Determine, based on a state of the shared memory buffer, to transfer contents of all occupied cells of the particular bank. Writes to the bank are stopped, contents of occupied cells are transferred to cells of one or more other banks associated with the particular bank's slice, information is stored indicating where the contents have been transferred, and the particular bank is returned to a shared pool after transferring is completed.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: May 8, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Sharad Vasantrao Chole, Shang-Tse Chuang, Georges Akis, Felice Bonardi, Rong Pan
  • Patent number: 9965192
    Abstract: Methods and systems for implementing a secure migratable architecture having improved performance features over existing virtualization systems are disclosed. One method includes allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method includes associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process, and receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor of the area descriptors, the request being associated with a plurality of memory addresses within the first memory area.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 8, 2018
    Assignee: Unisys Corporation
    Inventors: Andrew Ward Beale, David Strong
  • Patent number: 9959063
    Abstract: Described embodiments provide systems and processes for performing data migration in a storage system. One or more consistency groups are migrated from at least one source device to at least one target device in the storage system. The consistency groups are replicated from the source device to the target device by an asynchronous data replication operation from the source device to the target device and one or more synchronous data replication operations from the source device to the target device if data stored on the source device is changed. The consistency groups are operated on the source device and the target device in an active-active mode, wherein the source device and target device are active and accessible by host devices. Replicated consistency groups are determined to include in a cutover operation that is performed by deactivating the at least one source device associated with the included consistency groups.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 1, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: David Meiri, Aharon Blitzer
  • Patent number: 9959073
    Abstract: Described embodiments provide systems and processes for performing data migration in a storage system. One or more volumes are migrated from a source device to a target device in a storage system. A discovery state of the migrated volumes is determined by one or more host devices in communication with the storage system. An initiator group is configured for each host device. Each initiator group sends at least one inquiry to each of one or more volumes of the target devices. Responses to each inquiry from each volume are tracked. The system receives a selection of one or more migrated volumes to include in a cutover operation, the selection based at least in part upon the determined discovery states. One or more volumes of the source devices associated with the included volumes are deactivated.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 1, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: David Meiri
  • Patent number: 9952768
    Abstract: In one aspect, a multiple mode data structure can be utilized by a storage management system to provide a host representation role in one mode, and represent both a host and a host port in another mode. In one embodiment, in a first mode, the data structure has an undefined host port name attribute and a defined host name attribute to represent a host identified by the defined host name attribute. In the first mode, the data structure is restricted from representing a host port in the storage management system when the host port name attribute is undefined. In a second, unrestricted mode, the multiple mode data structure can represent both a host as well as a host port when a host port name attribute is defined. In one embodiment, the multiple mode data structure can also represent a host cluster. Other aspects are described.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua J. Crawford, Paul A. Jennas, II, Jason L. Peipelman, Matthew J. Ward