Abstract: A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.

Abstract: A memory device includes a non-volatile memory (NVM) array and a memory controller. The NVM array has four partitions in which each partition has as plurality of groups of NVM cells. The memory controller that performs a written operation on each of the four partitions in four cycles per group of NVM cells beginning a clock cycle apart in which two of the four clock cycles for the write operation are for an array write that requires a relatively high current and that the array write for each partition overlaps no more than one other array write so that a peak current of all four write operations is no more than twice the peak current of one group. The NVM cells may be magnetic tunnel junctions (MTJs) which have significantly faster written times than typical NVM cells.

Abstract: Provided are a computer program product, system, and method for assigning device adaptors to use to copy source extents in source ranks to target extents in target ranks in a copy relation. A determination is made of an order of the target ranks in the copy relation. Target ranks in the copy relation are selected according to the determined order. For each selected target rank, indication is made in a device adaptor assignment data structure of a source device adaptor and target device adaptor of the device adaptors to use to copy the source rank to the selected target rank indicated in the copy relation, wherein indication is made for the selected target ranks according to the determined order. The source ranks are copied to the selected target ranks using the source and target device adaptors indicated in the device adaptor assignment data structure.

Abstract: A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.

Abstract: Methods and corresponding systems for managing memory of a storage drive are provided. The method includes determining a number of invalid pages in each memory block of a plurality of memory blocks in the storage drive. Thereafter, the method includes identifying a set of target memory blocks within the plurality of memory blocks. The set of target memory blocks is identified by determining a target memory block comprising the highest number of invalid pages amongst the plurality of memory blocks. The step of determining is iterated to determine further target memory blocks while the total number of valid pages in the set of target memory blocks is less than or equal to the total number of free pages in one of at least one free memory block and a garbage collection memory block in the storage drive. The method further includes recycling the set of target memory blocks.

Abstract: The present invention relates to an interleaving and de-interleaving method, an interleaver and a de-interleaver. The interleaving method includes: receiving N×M frames of data, and sequentially storing, with each frame as a unit, the N×M frames of data in storage space indicated by N×M addresses of a first storage unit; transferring the data stored in the storage space indicated by an ((X?1)×M+Y+1)th address of the first storage unit to the storage space indicated by a (Y×N+X)th address of a second storage unit; and according to an address sequence, outputting the data stored in the space indicated by the N×M addresses of the second storage unit frame by frame. The interleaving and de-interleaving solutions of the present invention have low implementation complexity, and high capacity of correcting a burst bit error.

Abstract: Nodes in a distributed node system are configured to support memory corruption detection when memory is shared between the nodes. Nodes in the distributed node system share data in units of memory referred to herein as “shared cache lines.” A node associates a version value with data in a shared cache line. The version value and data may be stored in a shared cache line in the node's main memory. When the node performs a memory operation, it can use the version value to determine whether memory corruption has occurred. For example, a pointer may be associated with a version value. When the pointer is used to access memory, the version value of the pointer may indicate the expected version value at the memory location. If the version values do not match, then memory corruption has occurred.

Abstract: In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory location. In response to a probe seeking to take ownership of the shared memory location, the contention blocking buffer determines if the memory address indicated by the probe is stored at the contention blocking buffer. If so, the contention blocking buffer blocks the probe, thereby preventing another processor from taking ownership of the shared memory location.

Abstract: A storage device includes a first storage unit, a second storage unit, a third storage unit, and a processor. The first storage unit is configured to store therein a part of a data group stored in a storage system. The second storage unit is configured to store therein partial hierarchical information which is a part of information on a hierarchical structure of the data group. The third storage unit is configured to store therein owner information including a data identifier in association with a device identifier. The data identifier identifies a specific data included in the data group. The specific data is related to the partial hierarchical information. The device identifier identifies a specific storage device. The specific device stores therein the specific data. The processor is configured to share management of the data group with other storage devices on basis of the partial hierarchical information and the owner information.

Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.

Abstract: A method of migrating of an application from a source host to a destination host, wherein the application is associated with a plurality of memory pages, the source host comprises a first instance of the application and a source memory region, and each memory page has an associated source memory block in the source memory region, the method comprising: at the destination host, reserving a destination memory region such that each memory page has an associated destination memory block in the destination memory region, a second instance of the application at the destination host; on receipt of an input to the application, processing the input in parallel at the first and second instances at respective source and destination hosts: at the source host, if the processing requires a read or a write call to a memory page, respectively reading from or writing to the associated source memory block; the destination host, if the processing requires a write call to a memory page, writing to the associated destination memo

Abstract: An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

Abstract: Disclosed are a method for data de-duplication and an apparatus for the same. The method may comprise obtaining access property of data based on input request or output request for the data, determining de-duplication unit of the data based on the access property, and performing de-duplication on the data based on the de-duplication unit. Thus, data de-duplication rate may be determined adaptively based on input/output characteristics of data. Also, data de-duplication may be performed based on the determined data de-duplication rate so as to provide low input/output latency.

Abstract: An example method is provided for virtual machine data placement on a distributed storage system accessible by a duster in a virtualized computing environment. The method may comprise, based on location data relating to the cluster, identifying a first fault domain and a second fault domain of the distributed storage system. The method may further comprise selecting a first host with a first storage resource from the first fault domain and a second host with a second storage resource from the second fault domain. The method may further comprise placing a first copy of the virtual machine data on the first storage resource and a second copy of the virtual machine data on the second storage resource.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.

Abstract: An information processing apparatus, among a plurality of information processing apparatuses, to which one of pieces of local data is assigned, the pieces of local data having been obtained by dividing global data shared by the plurality of information processing apparatuses, includes: a storage unit that includes a first storage area sectioned into prescribed units, and stores local data; a processor that executes a process including: detecting a plurality of continuous sections to which the target local data is to be written in a second storage area that is sectioned into the prescribed units in the different information processing apparatus, on the basis of storage area information that identifies data to which the target local data corresponds in the global data; and extracting as many pieces of local data as specified by the number of the continuous sections and transmitting the data to the different information processing apparatus.

Abstract: A storage module may be configured to organize data to be moved from an initial storage location to a destination storage location into sets, and to determine whether to commit the data to the destination storage location on a set-by-set basis. Error correction and/or a post write and read process may be performed on the sets that are copied to the destination storage location to determine whether to commit each of the copied sets.

Abstract: A cache log module stores an ordered log of cache storage operations sequentially within the physical address space of a non-volatile storage device. The log may be divided into segments, each comprising a set of log entries. Data admitted into the cache may be associated with respective log segments. Cache data may be associated with the log segment that corresponds to the cache storage operation in which the cache data was written into the cache. The backing store of the data may be synchronized to a particular log segment by identifying the cache data pertaining to the segment (using the associations), and writing the identified data to the backing store. Data lost from the cache may be recovered from the log by, inter alia, committing entries in the log after the last synchronization time of the backing store.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.