Abstract: A region descriptor management method and an electronic apparatus are provided. The region descriptor management method is adapted to a device controller of the electronic apparatus and includes following steps. Region descriptor entries are fetched from a region descriptor table. Each of the region descriptor entries includes a block initial address and a block length to describe a memory block of a memory module. According to the block initial addresses and the block lengths of the region descriptor entries, a portion of the region descriptor entries are adjusted to be at least one current region descriptor entry. Based on the at least one current region descriptor entry, a current region descriptor table is generated.

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.

Abstract: System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements.

Abstract: A nonvolatile memory device includes a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs). The device determines whether a free block can be created by copying data between memory blocks of the first area. Upon determining that the free memory block can be created by copying data between the memory blocks of the first area, the device copies the data between the memory blocks of the first area to create the free memory block. Otherwise, the device selects at least one memory block from the first area and allocates the selected memory block as free memory block by copying the data stored in the selected memory block of the first area to the second area.

Abstract: Data placement for loss protection in a storage system includes constructing multiple logical compartments. Each logical compartment includes a placement policy including a set of storage placement rules for determining permitted placement of storage symbols, and a balancing policy for balancing placement of the storage symbols for each volume among physical storage containers. A first logical compartment of the multiple logical compartments is data loss independent with respect to a second logical compartment.

Abstract: A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

Abstract: A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.

Abstract: A method is provided for increasing data storage reliability in a heterogeneous storage system including multiple storage devices of different types. The devices store respective data subsets of a dataset. The method includes accessing configuration parameters for the dataset including first and second amounts of the data subsets respectively stored on the multiple storage devices. The method further includes estimating an initial global reliability of the heterogeneous storage system for the dataset, based on the configuration parameters. The method also includes determining an increased global reliability of the storage system for the dataset, by estimating a global reliability as would be obtained by modifying at least some of the configuration parameters, whereby at least the first and second amounts of the data subsets respectively stored on the devices are modified.

Abstract: A memory system capable of running a variety of different read retry sequences includes a memory controller that has a boot ROM with stored code for executing a read retry sequence. A non-volatile memory device such as a NAND flash includes a read retry register and receives command instructions including a read retry instruction from the memory controller and in response provides read data. A second non-volatile memory that is external to the NAND flash has a read retry table describing read retry sequence items that include a command, a read retry register address, and read retry data for updating the read retry register.

Abstract: The present invention provides a method of partitioning a tape medium dynamically by using a new method of writing data. It enables users to change size of the partitions later and to use all capacity of a tape efficiently. When a tape is divided into partitions, data is written in such a manner that the wraps are written in the partitions of the data band alternately in the forward direction and in the backward direction on the data band from the different sides of the data band toward the inside of the data band (W1,W2,W3 . . . ) and the location (C) at which the wrap (Wm) of the one partition collides with the wrap (Wn) of the other partition is defined as the demarcation (PB) of these partitions (P0,P1).

Abstract: A technique for garbage collection in a data storage system includes determining a dirty physical byte count for each of a plurality of candidate garbage collection units. The dirty physical byte count provides a total amount of dirty bytes. At least one of a dirty physical codeword container count and a dirty physical page count is determined for each of the candidate garbage collection units. The dirty physical codeword container count provides an amount of physical codeword containers that are completely dirty and the dirty physical page count provides an amount of physical pages that are completely dirty. A garbage collection unit, included in the candidate garbage collection units, is selected for garbage collection based on the dirty physical byte count and at least one of the dirty physical codeword container count and the dirty physical page count.

Abstract: Techniques and mechanisms for determining a timing of a command to access a memory device resource. In an embodiment, a multi-cycle command which is exchanged from a memory controller to a memory device, wherein the multi-cycle command indicates an access to a bank of the memory device. Timing of the one or more other commands is controlled, based on the multi-cycle command, to enforce a time delay parameter which describes an operational constraint of the memory device. In another embodiment, timing of one or more commands is determined with reference to a beginning of a last cycle of a multi-cycle command.

Abstract: A data protection method for a memory storage apparatus is provided. The method includes obtaining a current system time from a host system as a boot time, if the memory storage apparatus is powered on, and a basic input/output system of the host system loads and executes instruction programs in the expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus. The method also includes obtaining a shutdown time corresponding to the memory storage apparatus; calculating an off time from the shutdown time to the boot time and performing a refresh operation on physical erasing units of a rewritable non-volatile memory in the memory storage apparatus if the off time is longer than an off time threshold.

Abstract: According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.

Abstract: Disclosed are methods and systems of managing a plurality of storage devices having a lifetime of a finite number of operations. An average number of storage devices reaching said lifetime of a finite number of operations per first unit time is calculated. For each one of the plurality of storage devices an estimated date when a finite number of operations will be reached is calculated. For each date, a variable related to the number of storage devices reaching said finite number of operations within a predetermined period of said date is set. For one or more variables having a value larger than a value calculated using the date and said average number of storage devices reaching said lifetime within the predetermined period of said first unit of time, an action is carried out to reduce the number of storage devices reaching said lifetime per first unit of time.

Abstract: A method for improving access performance of a non-volatile storage device when programming data of a size smaller than a fixed minimum program number (FMPN) is disclosed. The method includes the steps of: predetermining a size of a blank data section for combining with a first data section and a second data section, the total size of the first data section, the second data section and the blank data section equals the FMPN; reading out data located at the second data section; updating a new data to the first data section; combining the new data with the data at the second data section; and incorporating the combined data with the blank data of the blank data section to become a final data, and programming the final data.

Abstract: In an embodiment, a processor includes hardware processing cores, a cache memory, and a compression accelerator comprising a hash table memory. The compression accelerator is to: determine a hash value for input data to be compressed; read a first plurality of N location values stored in a hash table entry indexed by the hash value; perform a first set of string searches in parallel from a history buffer using the first plurality of N location values stored in the hash table entry; read a second plurality of N location values stored in a first overflow table entry indexed by a first overflow pointer included in the hash table entry; and perform a second set of string searches in parallel from the history buffer using the second plurality of N location values stored in the first overflow table entry. Other embodiments are described and claimed.

Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Abstract: In an example, an analytic function to be performed on data stored in an input block is managed through an interface to a framework through which a user is to define the analytic function. The framework is to buffer batches of the data into a memory through implementation of a Reader, a Writer, a PreReader, and a PreWriter on the data stored in the input block when the user-defined analytic function is performed, and wherein the Reader, the Writer, the PreReader, and the PreWriter are individually movable with respect to each other in the input block. In addition, the user-defined analytic function is received through the interface.

Abstract: There is provided a storage arrangement and a method of operating thereof. The storage arrangement comprises a first storage system and one or more second storage systems operatively coupled to the first storage system. First control layer is operable to handle a first logical address space comprising a first logical group characterized by a plurality of logical block addresses; first control layer comprises a first mapping module handling a first mapping structure associated with first logical group. Each second control layer comprises, respectively, a second mapping module handling a second mapping structure associated with first logical group.