Abstract: The present application provides (in addition to more broadly applicable inventions) improvements which are particularly applicable to two-sided power semiconductor devices which use bipolar conduction. In this class of devices, the inventor has realized that two or three of the four (or more) semiconductor doping components which form the carrier-emission structures and control structures in the active device (array) portion of a two-sided power device can also be used, with surprising advantages, to form field-limiting rings around the active arrays on both surfaces. Most preferably, in some but not necessarily all embodiments, a shallow implant of one conductivity type is used to counterdope the surface of a well having the other conductivity type. This shallow implant, singly or in combination with another shallow implant of the same conductivity type, works to shield the well from the effects of excess charge at or above the surface of the semiconductor material.

Abstract: A device fabrication method includes: (1) providing a growth substrate including an oxide layer; (2) forming a metal layer over the oxide layer; (3) forming a stack of device layers over the metal layer; (4) performing fluid-assisted interfacial debonding of the metal layer to separate the stack of device layers and the metal layer from the growth substrate; and (5) affixing the stack of device layers to a target substrate.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, a first electrode which extends in a first direction and is surrounded by the first semiconductor layer except at one end thereof, and a first insulation film which is formed between the first semiconductor layer and the first electrode. A film thickness of the first insulation film between the other end of the first electrode in a second direction opposite to the first direction and the first semiconductor layer includes a thickness that is greater than a thickness of the first insulation film along a side surface of the first electrode. The semiconductor device also includes a second electrode which faces the second semiconductor layer, and a second insulation film which is formed between the second electrode and the second semiconductor layer.

Abstract: A method for obtaining a heterogeneous substrate intended for use in the production of a semiconductor comprises the following steps: (a) obtaining a first substrate (2) made from a type II-VI or type III-V material and a second substrate (1), each substrate being substantially planar and each substrate having a pre-determined surface area; (b) grinding a non-through recess (10) into the second substrate (1), the surface area of said recess being greater than the surface area of the first substrate, such that the first substrate can be housed in the recess; (c) depositing a bonding material (15) in the recess (10); (d) depositing the first substrate (2) in the recess (10) of the second substrate and securing the first substrate in the second substrate at a temperature below 300° C.; and (e) leveling the first and second substrates in order to obtain a heterogeneous substrate having a substantially planar face (30).

Abstract: Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.

Abstract: A method and apparatus are disclosed in which cadmium chloride is deposited on a cadmium telluride layer while simultaneously heat treating the cadmium telluride layer.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.

Abstract: A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors.

Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.

Abstract: A solid-state electronic device according to the present invention includes: an oxide layer (possibly containing inevitable impurities) that is formed by heating, in an atmosphere containing oxygen, a precursor layer obtained from a precursor solution as a start material including both a precursor containing bismuth (Bi) and a precursor containing niobium (Nb) as solutes, the oxide layer consisting of the bismuth (Bi) and the niobium (Nb); wherein the oxide layer is formed by heating at a heating temperature from 520° C. to 650° C.

Abstract: A polishing apparatus capable of monitoring an accurate progress of polishing is disclosed. The polishing apparatus includes: a polishing table for supporting a polishing pad; a table motor configured to rotate the polishing table; a top ring configured to press a substrate against the polishing pad to polish the substrate; a dresser configured to dress the polishing pad while oscillating on the polishing pad during polishing of the substrate; a filtering device configured to remove a vibration component, having a frequency corresponding to an oscillation period of the dresser, from an output current signal of the table motor; and a polishing monitoring device configured to monitor a progress of polishing of the substrate based on the output current signal from which the vibration component has been removed.

Abstract: A method of producing a solar cell, including: a first coating step in which a pre-wet composition is spin-coated on a surface of a semiconductor substrate; a second coating step in which a diffusing material including a solvent and a diffusing agent containing a first impurity element is spin-coated on the surface where the pre-wet composition has been spin-coated, so as to form a coating film of the diffusing agent; and a first impurity diffusion layer forming step in which the semiconductor substrate having the coating film formed thereon is heated, so as to form a first impurity diffusion layer in which the impurity element contained in the diffusing agent is diffused.

Abstract: The present disclosure relates to a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the BSI CSI has a semiconductor substrate with a front-side and a back-side. A plurality of photodetectors are located within the front-side of the semiconductor substrate. An implantation region is located within the semiconductor substrate at a position separated from the plurality of photodetectors. The implantation region is disposed below the plurality of photodetectors and has a non-uniform doping concentration along a lateral plane parallel to the back-side of the semiconductor substrate. The non-uniform doping concentration allows for the BSI CSI to achieve a small total thickness variation (TTV) between one or more photodetectors and a back-side of a thinned semiconductor substrate that provides for good device performance.

Abstract: Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the viaformed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.

Abstract: In a manufacturing method of a semiconductor device, a semiconductor chip is sealed with a resin, and then a laser is applied to remove the resin so that a part of the semiconductor chip is exposed. The semiconductor chip is made of a material that has a lower absorptivity of the laser than the resin and is not melted by the laser. The laser has a wavelength that passes through the semiconductor chip and has a lower absorptivity in the semiconductor chip than in the resin. The laser is applied to the resin from a side adjacent to one of plate surfaces of the semiconductor chip, so that the resin sealing the one of the plate surfaces is sublimated and removed and at least a part of the resin sealing the other of the plate surfaces is subsequently sublimated and removed by the laser having passed through the semiconductor chip.

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

Abstract: An image sensor operable in global shutter mode ma include small pixels with high charge storage capacity, low dark current, and no image lag. Storage capacity of a photodiode and a charge storage diode may be increased by placing a p+ type doped layer under the photodiode and the charge storage diode. The p+ type doped layer ma include an opening for allowing photo-generated charge carriers to flow from the silicon bulk to the charge storage well located near the surface of the photodiode. A compensating n? type doped implant may be formed in the opening. Image lag is prevented by placing a p? type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. The p+ type doped layer may extend under the entire pixel array.

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.