Abstract: An insulating film for embedding conductive portions therein is formed so as to represent convex configurations corresponding to each top of convex conductive portions. The insulating film is covered with an etching stopper film having an etching rate which is smaller than that of the insulating film. Convex portions of the etching stopper film corresponding to each top of the conductive portions are removed partially, thereby forming a contact hole that reaches each top of the conductive portions through the removal portions of the silicon nitride film by an etching treatment. A plug conductive portion connected to each top of the conductive portions is formed in the contact hole.

Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate.

Abstract: There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).

Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein a residual organic compound layer on the surface of a substrate is used to facilitate removal of unwanted encapsulant material. An organic compound layer which inherently forms on the substrate during the fabrication of the substrate or during various chip attachment processes is masked in a predetermined location with a mask. The substrate is then cleaned to remove the organic compound layer. The mask protects the masked portion of the organic material layer which becomes a release layer to facilitate gate break. An encapsulant mold is placed over the substrate and chip and an encapsulant material is injected into the encapsulant mold cavity through an interconnection channel. The release layer is formed in a position to reside as the bottom of the interconnection channel. Preferably, the interconnection channel has a gate adjacent the encapsulant mold cavity.

Abstract: A compensation ring 31 disposed to surround a periphery of a wafer W on a susceptor 30 is concentrically divided into an inside first compensation ring member 32 and an outside second compensation ring member 33. A width of a first compensation ring member 32 is made such thin as one to three times mean free path of treatment gas molecules, thereby suppressing heat transfer between a susceptor 30 and a second compensation ring member 33. A base of a second compensation ring member, through a layer of conductive silicone rubber 34, is made to come into an intimate contact with an upper surface of a susceptor 30, thus helping to cool.

Abstract: A method of manufacturing an optical semiconductor module, comprising joining an electronic cooling element to a bottom plate of an optical semiconductor package and mounting an optical semiconductor element on the electronic cooling element, wherein the electronic cooling element is soldered to the bottom plate of the optical semiconductor package in a hydrogen atmosphere. The soldering in a hydrogen atmosphere prevents oxidation of a low temperature solder provided on the uppermost surfaces of the electronic cooling element and conduction of the heat at the soldered joint portion between the electronic cooling element and the optical semiconductor element is improved.

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: A method for manufacturing integrated capacitive elements on a semiconductor substrate includes depositing a first metallization layer on a first dielectric layer. The first metallization layer includes a lower plate for a capacitive element and an interconnection pad. The method further includes forming a second dielectric layer over the first dielectric layer, forming a first opening aligned with the lower plate through the second dielectric layer, and depositing a third dielectric layer on the second dielectric layer and the lower plate and covering sidewalls of the first opening. A second opening is formed through the third dielectric layer and aligned with the interconnection pad. A fourth dielectric layer is deposited on the whole wafer surface, wherein the fourth dielectric layer is etchable in a completely selective manner relative to the third dielectric layer.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

Abstract: A present invention includes a packaging technology that fabricates build-up layers on an encapsulated microelectronic die that has expanded area larger than that of the microelectronic die. An active surface of a microelectronic die is attached by an adhesive material to a protective film sheet to protect the active surface and to control the position of the microelectronic die during an encapsulation process. The protective film sheet has adhesive material substantially only in an area where the microelectronic die and/or a microelectronic package core are attached, or has the adhesive properties of the adhesive material diminished or eliminated in areas where an encapsulation material will be applied.

Abstract: An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.

Abstract: A nickel silicide layer is formed on a semiconductor device having a crystalline silicon source/drain region doped with arsenic. Arsenic is doped into the crystalline silicon, by implantation, for example, so that the concentration of arsenic is slightly below the surface of the silicon. Annealing restores the crystalline structure of the silicon after implantation of the arsenic. Amorphous silicon is selectively deposited over the source/drain regions and over the top of the gate electrode. Nickel is deposited over the entire semiconductor device and a second anneal reacts the nickel with the amorphous silicon. The second anneal is timed so that the nickel reacts with the amorphous silicon, and does not substantially react with the silicon source/drain regions containing arsenic. Preventing the nickel from substantially reacting with the silicon source/drain regions containing arsenic provides a smooth interface between the resulting nickel silicide and the silicon source/drain regions doped with arsenic.

Abstract: In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a second impurity region formed in the substrate on a second side of the gate structure, the second impurity region including: a third impurity region of the first conductive type, a fourth impurity region of the first conductive type between the third impurity region and the second side of the gate structure, and a halo ion region of a second conductive type formed adjacent to the fourth impurity region.

Abstract: A coincidence detection circuit 42 is furnished to check whether a plurality of output signals read from a plurality of memory cell arrays CELL0 through CELL3 coincide with one another. A representative output buffer 36 is provided to have the output signal from the cell array CELL0 reach a representative pin DQ0 if the output signals are judged to coincide with one another, and to block the output signal from the cell array CELL0 while putting the representative pin DQ0 in a high-impedance state if the output signals are not judged to coincide. Input/output pins DQ1 through DQ3 are furnished with ordinary output buffers 32.

Abstract: Aspects for detecting integrated circuit package orientation in carrier tape packing are described. In accordance with these aspects, a digital circuit is provided over a carrier rail of a tape and reel system. The digital circuit detects package orientation based on a chamfer side of packages within a tape on the carrier rail. The digital circuit further includes at least two optical sensors, where the optical sensors emit a light beam and sense reflection of the light beam for each package within the tape for use in determining package orientation in an automated manner.

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar.

Abstract: To shorten a process for manufacturing a semiconductor device comprising a silicide and a non-silicide diffusion layers and to form a stable and highly homogenous non-silicide diffusion layer, ions are implanted to form a source/drain diffusion layer and then the substrate is subjected to rapid thermal oxidation in a short time to activate the ions while forming a new oxide film. A thermal oxide film (6) consisting of the new oxide film including a protective oxide film (3) is etched to form an oxide film for preventing silicidation (8), a Ti film (9) is formed over the whole surface including the oxide film for preventing silicidation (8), the product is annealed for silicidation and the unreacted Ti film (9) is removed. Thus, a diffusion layer (4) as a non-silicide layer which is little silicided and a diffusion layer (5) whose surface is a silicide layer (10) are formed.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.