Abstract: In forming a plug 21 of a polycrystalline silicon film in a contact hole 19 to which a bit line BL is connected, the upper surface of the plug 21 is retracted downward from the upper edge of the contact hole 19, and a plug 22 of a laminate of a TiN film 26 and a W film 27 is formed on the plug 21. Then, the W film deposited on the contact hole 19 is patterned to form a bit line BL having a width narrower than the diameter of the contact hole 19. Here, the W film 27 constituting part of the plug 22 in the contact hole 19 is etched, but the TiN film 26 constituting another part of the plug 22 is not almost etched.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, and the conductive trace includes a contact terminal that extends through the insulative base, then forming an opening that extends through the metal base and the insulative base, exposes the pad and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

Abstract: A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

Abstract: A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

Abstract: Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analog device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as “conductive plug/conductive layer pattern”.

Abstract: A high voltage integrated switching device includes at least one high voltage switching circuit, preferably employing DMOS technology and characterized by a breakdown voltage of at least 100 volts, on a dielectrically isolated, bonded and vertically trenched silicon substrate. Multiple high-voltage switching circuits may be located in close proximity on a single substrate without circuit breakdown or shorting during circuit operation. The circuit may further include one or more low- and/or intermediate-voltage circuits employing, for example, CMOS and bipolar technologies on the same silicon substrate and located in close proximity without voltage breakdown during circuit operation.

Abstract: The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a doped central part (140), located between the source and drain regions, and separated from said source and drain regions.

Abstract: A method of manufacturing micro-display includes the steps of testing individual chips on a base wafer forming the micro-display, and the tested “void” chips being marked, inputting the testing data into a sealant/glue machine and a laser puncher; sealant/glue forming on the external surrounding of a “passed” chip a sealant frame by the sealant/glue machine; forming an injection hole on an ITO glass panel at a position corresponding to the position of the “passed” chip, by means of the laser puncher; dispensing spacing particles within a chip's square box which has been formed with the sealant frame; position-aligning the ITO glass panel onto the wafer based on the wafer testing data; injecting a liquid crystal via the injection hole of the ITO glass panel located on the top layer of the “passed” chip to the space between the chips and the ITO glass; and sealing and dicing handling of the ITO glass panel to precisely manufacture the micro-display with a pas

Abstract: Disclosed is a thin-layer solar cell array system and a method for producing the same, having placed over a carrier substrate of plane design, a solar cell layer which is provided with at least one n-type conducting semiconductor zone (emitter) and at least one p-type conducting semiconductor zone (base) as well as a first and a second contact electrode, each of different electric polarity, which are each electrically connected to the emitter respectively to the base.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.

Abstract: A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Hafnium (or hafnium-zirconium) nitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, an insulative adhesive and a hardened connection joint. The conductive trace includes first and second opposing surfaces and a peripheral sidewall between the surfaces, the first surface faces away from the pad and the peripheral sidewall overlaps the pad. The adhesive is between the second surface and the pad. The connection joint contacts the first surface, the peripheral sidewall and the pad, extends between the peripheral sidewall and the pad and electrically connects the conductive trace and the pad. Preferably, the connection joint is reflowed solder or cured conductive adhesive. A method of manufacturing the assembly includes disposing the adhesive between the conductive trace and the pad, then etching the adhesive thereby exposing the pad, then depositing a non-solidified material on the first surface, the peripheral sidewall and the pad, and then transforming the non-solidified material into the connection joint.

Abstract: The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

Abstract: A circuit element that includes a ferroelectric device connected to a substrate device. The circuit element is constructed by fabricating the substrate device in a semiconductor substrate and depositing a dielectric layer over the semiconductor substrate. A via is then etched in the dielectric layer to provide access to the substrate device and filled with copper or tungsten. A layer of a conducting metallic oxide is then deposited on the conducting plug, and a layer of ferroelectric material is deposited on the layer of conducting metal oxide. The layer of conducting metallic oxide is deposited at a temperature below 450° C., preferably at room temperature.

Abstract: A method and apparatus thereof for fabricating an integrated circuit on a laminate having a gate electrode layer over a silicon dioxide layer. Detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material (e.g., n-type dopant) and minimizing the use of a slower etching dopant material (e.g., p-type dopant) in the gate electrode layer. In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. The remaining portion of the gate electrode layer is doped with the faster etching dopant material; thus, more of the gate electrode layer is doped with the faster etching dopant material than with the slower etching dopant material. A gate mask is aligned over the gate electrode layer, and the unmasked portions of the gate electrode layer are removed using an etchant.

Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract: A method of fabricating a compound semiconductor device having an ohmic electrode of a low contact potential includes a first cleaning step of heating a compound semiconductor substrate containing a first conductivity type impurity in a temperature range of not more than 250° C. and etching its surface with hydrogen chloride at the temperature of not more than 250° C., and a second cleaning step of performing a radical hydrotreatment on the compound semiconductor substrate at a temperature not more than 250° C., after the first cleaning step. The first cleaning step removes an oxide film but leaves chlorine on the surface of the substrate. The second cleaning step removes the chlorine. The temperature of not more than 250° C. avoids damaging other layers such as an active layer on the opposite surface of the substrate.

Abstract: An active anti-ESD pod for transporting photomask (reticle) comprises six body portions delimiting the container, an electrically conducting plate on the top portion, and an electrically conducting handle connected to the plate. An active charge sinker combined with a tag identifying the container or placed onto the photomask itself is provided to absorb the static electricity and to thus prevent charge accumulation that may otherwise cause ESD damage to the photomask.