Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: Methods for fabricating plastic molded thermally enhanced flip chip packages in which the heat spreaders are assembled in strip format is disclosed, including the first step of providing the heat spreader strip. Inclusion of heat spreaders in strip format allows better automation of the molding process using equipment and fabrication technology known in the industry, and provides a cost effective solution to assembly of high density area array packages. The design of heat spreaders include reduced cross section connecting straps which are readily severed and leave only a small plastic to metal interface for ingress of contamination. Further the designs comprehend either embedded or exposed heat spreaders with methods to hold securely during the molding process.

Abstract: A method and structure for reducing mechanical shear stresses induced in an IC chip by metal interconnect lines that interconnect the chip with its surrounding substrate. A dielectric layer overlies at least a portion of the substrate and a peripheral surface region of the chip. The lines are formed on the dielectric layer and are electrically interconnected with contact pads on the peripheral surface region of the chip, i.e., beneath the dielectric layer. At least one trench is formed in the dielectric layer and surrounds the peripheral surface region of the chip. The lines traverse the trench so as to have nonplanar portions within the trench. The trenches and the nonplanar portions of the lines increase the expansion/contraction capability of the dielectric layer and lines in a region sufficiently close to where the lines are interconnected to the contact pads, such that shear stresses at critical points near the line-pad connections are significantly reduced.

Abstract: Testing is performed on a semiconductor die (50) having a plurality of protruding electrical contacts (52) formed thereon. The test method uses a carrier (100) having a plurality of wells (110) formed in a dielectric layer (118) thereon. At least a portion of the protruding electrical contacts (52) is inserted into a corresponding portion of the plurality of wells (110) in order to make electrical connections between the semiconductor die (50) and the carrier (100) with minimal damage to the protruding electrical contacts (52). Testing (e.g. functional testing, burn-in testing, full-speed testing) of the semiconductor die (50) may then be performed using the electrical connections. Once testing of the semiconductor die (50) is completed, the semiconductor die (50) is removed from the carrier (100) and the carrier (100) may be reused for testing a different semiconductor die.

Abstract: A method for manufacturing a diffusion barrier layer over a substrate having a patterned copper layer. A refractory metal layer is formed on the substrate and a top surface and a sidewall of the patterned copper layer. The refractory metal layer is converted into an implanted layer as a diffusion barrier layer, where gas of N2, O2, or N2O are used for producing implanting ions. A thermal process is performed to stabilize a diffusion barrier quality of the oxygen-containing implantation layer.

Abstract: There is disclosed herein a method for scribing the top electrode of semiconductor devices. According to the method, a scribe region of the top electrode is defined by creating a high electrical resistance perimeter there around. A channel having relatively high electrical conductivity is formed between the scribe region of the top electrode and the bottom electrode of the device. The device is then subjected to an electroconversion process wherein a current flow via the conductive path, and through the scribe region of the electrode, causes the bath to render the top electrode material in the scribe area nonconductive.

Abstract: The present invention relates to a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, that around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.

Abstract: A method for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display and a method of constructing the same, wherein the transistor has a gate, a source and a drain, and a gate insulator between the gate and an active silicon layer. The improvement is a layer of the ammonia-free silicon nitride deposited between the copper,aluminum, or other refractory metal gate and the gate insulator. Further,. the gate is copper, aluminum, or another refractory metal and is deposited directly on the substrate. The layer of ammonia-free silicon nitride is also deposited on portions of the substrate adjacent the gate and the gate line extending therefrom. The layer is made in a plasma-enhanced chemical vapor deposition process wherein the gas mixture comprises one part silane to 135 parts nitrogen to 100 parts helium and 100 parts hydrogen.

Abstract: The dual damascene method having steps of; after a first insulating film, a first organic insulating film, a second insulating film, and a metal film are formed in sequence, a first opening having a wiring pattern is formed in the metal film, then a second opening having a via pattern is formed in the second insulating film, then the first organic insulating film is etched using the second insulating film as a mask, then the first insulating film and the second insulating film are etched simultaneously while using the metal film and the first organic insulating film as a mask, and then the first organic insulating film is etched while using the metal film as a mask, at this stage, a wiring recess is formed in the first organic insulating film and the second insulating film, and a via-hole is formed in the first insulating film.

Abstract: Structures and methods are described that inhibit atomic migration which otherwise creates an undesired capacitive-resistive effect arising from a relationship between a metallization layer and an insulator layer of a semiconductor structure. A layer of an inhibiting compound may be used to inhibit a net flow of atoms so as to maintain conductivity of the metallization layer and maintain the low dielectric constant of a suitable chosen insulator material. Such a layer of inhibiting compound continues to act even with the reduction of ground rules in succeeding generations of semiconductor processing technology. One embodiment includes an insulator having a first substance, wherein the first substance is selected from a group consisting of a polymer and an insulating oxide compound. The embodiment includes an inhibiting layer on the insulator, wherein the inhibiting layer includes a compound formed from a reaction that includes the first substance and a second substance.

Abstract: In accordance with one aspect of the invention, a semiconductor processing method of treating a semiconductor wafer provides a wafer within a volume of liquid. The wafer has some electrically conductive material formed thereover. The volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere and at a temperature of at least 200° C. and below and within 10% of the melting point of the electrically conductive material. In accordance with another aspect, the volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere. After establishing the pressure of greater than 1 atmosphere, the pressure of the volume of liquid is lowered to a point effective to vaporize said liquid and the vapor is withdrawn from the chamber.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for milling the substrate of a semiconductor device and exposing a selected region in the substrate. A laser is directed at a selected area of the back side of the device to create a small marker to be used for alignment during the milling process. The substrate is then milled to expose the selected area within the substrate, using the marker as alignment.

Abstract: A method for forming an interlayer insulating film is disclosed. This method comprises the steps of: forming an Si—C film or an Si—C—H film on an underlying insulating film by performing plasma polymerization for an Si and C containing compound; forming a porous SiO2 film by performing O (oxygen) plasma oxidation for the Si—C film or the Si—C—H film; and forming a cover insulating film on the porous SiO2 film by performing H (hydrogen) plasma treatment for the porous SiO2 film.

Abstract: A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.

Abstract: A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.

Abstract: An article is disclosed having a non-planar surface with a high-resolution pattern formed thereon, particularly a distributed-feedback (DFB) ridge waveguide laser. An elastomeric member having relief patterns on its surface is used to print or mold a pattern directly onto the non-planar surface of the waveguide. A range of materials disposed on such non-planar surfaces can thus be patterned at high resolution to provide devices with sub-micron features at low cost with potential applications in optoelectronics. For example, a plastic laser based on molded organic gain materials may be made.

Abstract: A substrate processing method of processing a surface of a substrate in manufacture of a semiconductor device, characterized by comprising a surface processing step for making a substance having an adsorption heat higher than that of an organic matter whose adsorption on the surface of the substrate, which has been cleaned, is undesirable, adsorbed on the surface of the substrate, and a film formation step for forming a thin film on the surface of the substrate which was processed in the above step.

Abstract: A resist coating and developing processing apparatus comprises an airflow forming mechanism for forming airflows from the tops of a cassette station, a processing station, and an interface section toward the bottoms and a controller for controlling the airflow forming mechanism, in which the processing station includes draft openings communicating with the cassette station and the interface section respectively. The controller controls the airflow forming mechanism so that the pressure in the processing station becomes higher than the pressures in the cassette station and the interface section to form flows of air from the processing station into the cassette station and the interface section. Thereby, influence of impurity components such as particles, alkaline components, and the like and changes in atmosphere such as temperature, humidity, and the like exerted on processing can be effectively precluded.

Abstract: Fabrication of a polysilicon TFT having a lightly doped drain or offset structure. Fabrication includes forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate. Then, forming lightly doped impurity regions in the semiconductor layer on both sides of the gate electrode. Next, forming an insulating film having a thickness that gradually becomes thinner away from the gate electrode. Then, forming heavily doped impurity regions in the lightly doped impurity regions in the semiconductor layer on both sides of the gate, resulting in regions with continuously varied impurity concentrations.

Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure includes a field-effect transistor having amorphized source and drain regions formed by implanting silicon or germanium ions into a silicon layer formed over a buried insulator. The fully amorphized source and drain regions ultimately result in permanent crystalline defects that cause p-n junction leakage which allows charge in the body of the device to dissipate, thereby improving the overall efficiency and performance of the device. The source and drain regions are amorphized throughout their entire thickness to prevent single crystal re-crystallization from occurring during annealing and other subsequent processing steps that can degrade the quality of the p-n leakage junctions.