Patents Examined by Richard A. Booth
  • Patent number: 11362185
    Abstract: A method for manufacturing a memory device is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Yen-Di Wang, Jia-Yang Ko, Men-Hsi Tsai
  • Patent number: 11355578
    Abstract: We disclose herein a high voltage device comprising: a first electrode; a second electrode disposed underneath and spaced from the first electrode; and a dielectric layer disposed between the first and second electrodes, wherein the first electrode extends further in at least one lateral direction in respect of the second electrode.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 7, 2022
    Assignee: X-FAB DRESDEN GMBH & CO.KG
    Inventors: Victor Sizov, Denis Reso
  • Patent number: 11355643
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: June 7, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11348876
    Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Seung-Kwan Ryu, Seokhyun Lee
  • Patent number: 11349031
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: May 31, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11342344
    Abstract: The present disclosure relates to a memory device, and more particularly, to a memory device including a substrate, a plurality of vertical structures disposed on the substrate and including insulation layers and lower electrodes, which are alternately laminated with each other, wherein the vertical structures are aligned in a first direction parallel to a top surface of the substrate and a second direction crossing the first direction, an upper electrode disposed on a top surface and side surfaces of each of the vertical structures, and a first dielectric layer disposed between the upper electrode and the vertical structures to cover the top surface and the side surfaces of each of the vertical structures. Here, the first dielectric layer includes a ferroelectric material.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 24, 2022
    Assignees: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Seungeon Moon, Bae Ho Park, Sung-Min Yoon, Seung Youl Kang, Jeong Hun Kim, Jiyong Woo, Jong Pil Im, Chansoo Yoon, Ji Hoon Jeon
  • Patent number: 11342423
    Abstract: A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 24, 2022
    Assignee: II-VI DELAWARE, INC.
    Inventors: Adolf Schöner, Sergey Reshanov, Nicolas Thierry-Jebali, Hossein Elahipanah
  • Patent number: 11329158
    Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: May 10, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Halting Wang, Judson R. Holt, Sipeng Gu
  • Patent number: 11322507
    Abstract: A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 3, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Jack Sun, Xian Liu, Leo Xing, Nhan Do, Andy Yang, Guo Xiang Song
  • Patent number: 11322597
    Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 3, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hokuto Kodate, Hiroyuki Ogawa, Dai Iwata, Mitsuhiro Togo
  • Patent number: 11316020
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending form the base to the first major surface, and a field plate arranged in the trench and an enclosed cavity in the trench. The enclosed cavity is defined by insulating material and is laterally positioned between a side wall of the field plate and the side wall of the trench.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sylvain Leomant, Georg Ehrentraut, Maximilian Roesch
  • Patent number: 11316042
    Abstract: A superjunction device comprising a drain contact, a substrate layer above the drain contact, an epitaxial layer above the substrate layer, a P+ layer above the epitaxial layer formed by P-type implantation to a bottom of the superjunction device, a trench with a sloped angle formed by use of a hard mask layer. The trench is filled with an insulating material. A first vertical column is formed adjacent to the trench. A second vertical column is formed adjacent to the first vertical column. A source contact is coupled to the first vertical column and the second vertical column. A P-body region is coupled to the source contact. A gate oxide is formed above the source contact and the epitaxial layer, and a gate formed above the gate oxide.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 26, 2022
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: Alexei Ankoudinov, Sorin S. Georgescu
  • Patent number: 11309407
    Abstract: A method of manufacturing a low temperature polysilicon thin film includes: forming a buffer layer on a substrate; forming a gate electrode on the buffer layer; forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode; forming a first diffusion barrier layer on the patterned raising layer; forming a second diffusion barrier layer on the first diffusion barrier layer; forming a silicon layer on the second diffusion barrier layer; annealing the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer; and in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 19, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Huailiang He
  • Patent number: 11302528
    Abstract: A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 12, 2022
    Assignee: PSIQUANTUM, CORP.
    Inventors: Yong Liang, Vimal Kumar Kamineni
  • Patent number: 11302697
    Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 12, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Andrew J. Walker, Dafna Beery, Peter Cuevas, Amitay Levi
  • Patent number: 11292714
    Abstract: A physical quantity sensor includes a movable body, a support portion supporting the movable body through a connecting portion, and a substrate that is disposed so as to overlap the movable body in plan view and provided with a first fixed electrode and a second fixed electrode along a first direction orthogonal to a longitudinal direction of the connecting portion. In plan view, a dummy electrode that is disposed next to the first fixed electrode and is at the same potential as the movable body is provided on the substrate. The first fixed electrode and the dummy electrode includes a first electrode material layer provided on the substrate, and a second electrode material layer provided on the substrate and on the first electrode material layer.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 5, 2022
    Inventor: Satoru Tanaka
  • Patent number: 11296099
    Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Fu-Chen Chang, Chih-Hsiang Chang, Sheng-Hung Shih
  • Patent number: 11296228
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 5, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11289608
    Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 29, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Ramesh Ramamoorthy, Sasikanth Manipatruni, Gaurav Thareja
  • Patent number: 11289509
    Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov