Abstract: An apparatus for manufacturing a display device includes a stage, a first electric field applying module including first probe pins and disposed on a first side of the stage, a light irradiation module including light-emitting elements and disposed on the stage, and a first voltage output module that outputs an emission driving signal that drives the light-emitting elements, outputs a first alignment signal to one of the first probe pins, and outputs a second alignment signal to another one of the first probe pins.

Abstract: Ferroelectric materials and more particularly cerium-doped ferroelectric materials and related devices and methods are disclosed. Aspects of the present disclosure relate to ferroelectric layers of hafnium-zirconium-oxide (HZO) doped with cerium that enable reliable ferroelectric fabrication processes and related structures with significantly improved cycling endurance performance. Such doping in ferroelectric layers also provides the capability to modulate polarization to achieve a desired operation voltage range. Doping concentrations of cerium in HZO films are disclosed with ranges that provide a stabilized polar orthorhombic phase in resulting films, thereby promoting ferroelectric capabilities. Exemplary fabrication techniques for doping cerium in HZO films as well as exemplary device structures including metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) structures are also disclosed.

Abstract: Provided are a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a substrate and a plurality of pixel units disposed in matrix on the substrate, wherein each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a driving structure layer, a first electrode and a first pixel define layer on the driving structure layer, and a light absorption layer disposed on the first pixel define layer. The first pixel define layer includes a plurality of first barriers and first pixel openings disposed between the first barriers, the first pixel opening exposes at least part of the first electrode, and the first pixel opening includes a first surface close to the first electrode, a second surface opposite to the first surface and a first sidewall between the first and second surfaces.

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

Abstract: The present application relates to a capacitor device and a manufacturing method thereof, and a memory. forming a first capacitor structure on a substrate, includes: a first capacitor dielectric layer, a first upper electrode, a plurality of first lower electrodes arranged at intervals; the first capacitor dielectric layer at least covers sidewalls of the first lower electrodes, and the first upper electrode fills up gaps at an outer side of the first capacitor dielectric layer; forming a second capacitor structure on the first capacitor structure, the second capacitor structure includes a second capacitor dielectric layer, a second upper electrode, and a plurality of second lower electrodes arranged at intervals; the second lower electrodes are of a U-shaped structure, bottoms of the second lower electrodes are in contact with tops of the first lower electrodes, the second capacitor dielectric layer is at least located on surfaces of the second lower electrodes.

Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.

Abstract: A manufacturing method for a semiconductor structure includes: a substrate is provided, the substrate including a first region and a second region; a dielectric layer is formed on the substrate; a first diffusion film layer having a first metal oxide layer is formed on the dielectric layer; the first diffusion film layer corresponding to the second region is removed; a second diffusion film layer is formed on the dielectric layer corresponding to the second region, the second diffusion film layer including a second metal oxide layer interfacing with the dielectric layer; and an annealing treatment is performed to diffuse a first metal element in the first metal oxide layer into the dielectric layer corresponding to the first region and diffuse a second metal element in the second metal oxide layer into the dielectric layer corresponding to the second region.

Abstract: A memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. The semiconductor substrate has a first active region. The first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. The dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. The control gate electrode is over the dielectric layer. The control gate electrode is in contact with the first and second portions of the dielectric layer.

Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.

Abstract: A device including a first transistor, having a gate region partially penetrating into a gallium nitride layer, and a second transistor located inside of the gate region of the first transistor.

Abstract: The present disclosure relates to a camera package, a method for manufacturing a camera package, and an electronic device with which it is possible to reduce manufacturing cost for lens formation. The camera package according to the present disclosure includes: a solid-state imaging element; and a lens formed above a transparent substrate that protects the solid-state imaging element. A lens formation region in which the lens is formed above the transparent substrate and a lens free region around the lens formation region differ in contact angle. The present disclosure can be applied to, for example, a camera package in which a lens is disposed above a solid-state imaging element, or the like.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: A manufacturing method of a semiconductor structure includes forming a dielectric layer stack including a first oxide layer and a second oxide layer over the first oxide layer. An opening is formed in the dielectric layer stack, and includes a first portion exposing sidewalls of the first oxide layer and a second portion exposing sidewalls of the second oxide layer. A sacrificial layer is formed over the dielectric layer stack and along the sidewalls of the first oxide layer and the second oxide layer in the opening. A first etching is performed to remove the sacrificial layer along the sidewalls of the first oxide layer. A second etching is performed to widen the first portion of the opening. The sacrificial layer along the sidewalls of the second oxide layer and over the dielectric layer stack is removed. A capacitor is formed in the opening after removing the sacrificial layer.

Abstract: A method for manufacturing a vertical blue light emitting diode (LED) includes: bonding a growth substrate to a conductive substrate; peeling off the growth substrate; etching the nitride epitaxial layer to remove the buffer layer and the undoped GaN layer and to thin the N-type GaN layer, such that a thickness of a residual nitride epitaxial layer is less than a wavelength of blue light; and forming an N-type electrode on a surface of a residual N-type GaN layer.

Abstract: A semiconductor structure includes a substrate, a storage capacitor unit, a transistor, and an electrical connection structure. The storage capacitor unit is located at an array area and includes: N insulation posts, distributed in a direction parallel to a surface of the substrate; a bottom electrode layer; a top electrode layer, directly facing the bottom electrode layer; and a capacitor dielectric layer, located between the top and bottom electrode layers. One of the bottom or top electrode layers corresponding to the N insulation posts is a continuous film layer, and the other is discrete film layers. The transistor is located at a circuit area and includes a capacitor control terminal located in the substrate of the circuit area. The electrical connection structure is electrically connected to the capacitor control terminal, and extends from the circuit area to the array area to come into contact with a corresponding discrete film layer.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

Abstract: A semiconductor structure and a method for manufacturing same. The semiconductor structure includes: a semiconductor base, including a logical device region and a memory region; a bit line located in the memory region and an electrical contact layer located in the logical device region, which are disposed in a same layer; a first semiconductor channel located on the bit line and a second semiconductor channel located on the electrical contact layer, which are disposed in a same layer; a word line and a gate disposed in a same layer; a capacitor structure, in contact with a second doped region of the first semiconductor channel; an electrical connection structure, in contact with the fourth doped region of the second semiconductor channel; and a dielectric layer, located between the bit line and the word line, and on a side of the word line away from the semiconductor base.

Abstract: A vertical blue LED includes: a conductive substrate, the conductive substrate including a first surface and a second surface opposite to the first surface a nitride epitaxial layer; a metal reflective layer, positioned on the first surface; a nitride epitaxial layer, positioned on a surface of the metal reflective layer and including a P-type GaN layer, a quantum well layer, a preparation layer, and an N-type GaN layer that are sequentially stacked along a direction perpendicular to the conductive substrate, wherein a thickness of the nitride epitaxial layer is less than a wavelength of blue light; an N-type electrode, positioned on a surface of the N-type GaN layer; and a P-type electrode, positioned on the second surface.