Abstract: A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.

Abstract: A semiconductor device includes a first region that contains a first conductive type impurity and is provided on a substrate, a second region that is provided in the first region and contains the first conductive type impurity at a higher concentration than the first region, a first structure that is provided on the substrate on one side of the second region in a first direction along the substrate and has a first sidewall at least on the second region side, a second structure that is provided on the substrate on the other side of the second region in the first direction and has a second sidewall at least on the second region side, and a contact that passes between the first and second sidewalls facing each other across the second region, extends to the second region, and is electrically connected to the second region.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.

Abstract: A semiconductor structure includes a semiconductor substrate, a serpentine-shaped resistor, and a MOS transistor. The semiconductor substrate includes an isolation structure and an active region. The serpentine-shaped resistor is over the isolation structure. The serpentine-shaped resistor extends in a length direction and has a width that is equal to or greater than about 3.6 ?m in a width direction. The MOS transistor is over the active region of the semiconductor substrate.

Abstract: A semiconductor device includes conductive patterns, an insulating pattern between the conductive patterns, an insulating etch stop layer on the conductive patterns and the insulating pattern, a capacitor including first electrodes in contact with the first conductive patterns, a second capacitor electrode, and a dielectric between the first and second capacitor electrodes, an insulating structure covering the capacitor and the insulating etch stop layer, and a peripheral contact plug through the insulating structure and the insulating etch stop layer and including first through fifth plug regions stacked on top of each other, at least a portion of a side surface of the fourth plug region having an inclination angle different from inclinations angles of the third and fifth plug regions, and a vertical thickness of the fifth plug region being at least twice as great as a sum of vertical thicknesses of the first to fourth plug regions.

Abstract: A noble metal liner and a metal-insulator-metal (MIM) capacitor (MIMCAP) are described along with the methods of manufacture or fabrication. The MIM capacitor includes a liner formed of a thin layer or film of a noble metal, which is only a few nanometers thick, e.g., a thickness in the range of about 0.5 nm to about 5 nm or more. In a finished device such as a MIM capacitor, the noble metal liner is sandwiched between a thicker electrode and the insulator, e.g., a layer or thin film of high or ultra high-k material, thereby providing a cap for the electrode to limit leakage currents in the device.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: The present application discloses a method for making an active area air gap, comprising: step 1, performing word line etching to form a plurality of word line structures on a semiconductor substrate, wherein each word line structure spans each field oxide and each active area; step 2, forming a protective spacer on a side surface of the word line structure in a self-aligned manner; step 3, etching the field oxide by means of isotropic etching, so as to lower the top surfaces of the field oxides within and outside a coverage area of the word line structure and thus form an active area air gap between the active areas, wherein the word line structure spans the active area air gap; and step 4, removing the protective spacer.

Abstract: A system and apparatus for direct or indirect target substance signal measurement include an integrated circuit with an array of 2D FETs with corresponding 2D transistor channels and a gate area for receiving a volume of liquid with one or more chemical or biological target substances, a conductive source electrically coupled to a first end of the 2D transistor channel, a conductive drain electrically coupled to a second end of the 2D transistor channel, a ceramic coating over the conductive source and the conductive drain and a thin film layer of synthetic biopolymer specific binding agents is adsorbed to the top surface of the 2D transistor channel. Methods for the system and apparatus and for selecting the synthetic biopolymer specific binding agents based on absorptivity are disclosed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

Abstract: Embodiments of the present disclosure belong to the technical field of semiconductor structure manufacturing, and specifically provide a semiconductor structure and a manufacturing method thereof. The manufacturing method specifically includes: a first gate structure on a substrate, a first conductive region and a second conductive region, wherein the first conductive region and the second conductive region are located at two sides of the first gate structure, and in a direction perpendicular to the substrate, the first conductive region and the second conductive region are located at different height positions.

Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.

Abstract: A semiconductor storage device includes a plurality of wiring layers stacked in a first direction, a memory pillar penetrating the plurality of wiring layers in the first direction, and a semiconductor layer provided in the memory pillar and extending in the first direction. The semiconductor storage device further includes a wiring layer that extends in a second direction crossing the first direction, is provided above the plurality of wiring layers, and penetrates the semiconductor layer.

Abstract: Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: A GaN-based compound semiconductor device includes a GaN-based epitaxial structure and an annealed metal layered structure that is formed on the GaN-based epitaxial structure. The annealed metal layered structure includes a metallic barrier layer, a conductive unit, and a protective unit which is formed on a lateral surface of the conductive unit. The metallic barrier layer and the conductive unit are sequentially disposed on the GaN-based epitaxial structure in such order. An ohmic contact is formed between the GaN-based epitaxial structure and the annealed metal layered structure. The protective unit includes a metal oxide material having one of NiAlO, AuAlO, and a combination thereof.

Abstract: There is provided a technique capable of improve the uniformity of the film formed on the substrate. According to one aspect of the technique, there is provided a substrate processing method includes: (a) setting a substrate at a first position such that a distance between the first position and a gas supply port of a film-forming auxiliary gas supplier is a first distance, and causing a film-forming auxiliary gas to be adsorbed onto the substrate by supplying the film-forming auxiliary gas to the substrate; and (b) moving the substrate to a second position such that a distance between the second position and a gas supply port of a source gas supplier is a second distance different from the first distance, and forming a film of a predetermined thickness on the substrate by supplying a source gas.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.