Abstract: The invention enables plural computers to initiate operation of respective operating systems through use of a shared operating system kernel. A system embodying the invention includes a central storage unit (e.g. a disk drive) that includes an operating system kernel, and plural computers, each computer including memory for holding an initiation boot code that enables initial startup of the respective computer upon a power up or a reset. A channel communication link provides circuit connections between the central storage unit and each of the plural computers. Each of the plural computers responds to a power-up or reset action by initiating operation of respective ones of the boot codes. Each boot code, after initiating preliminary operations, performs an access of the operating system kernel from the central storage unit via the channel communication circuit so as to enable a high speed load of the kernel to the respective computer memories.

Abstract: A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.

Abstract: Disclosed is a method and apparatus for software configuration of a processor clock ratio. Boot code that the processor executes in response to a reset event correctly configures the clock ratio to a desired value, where the desired value can be set via a user interface. The processor then checks the clock ratio against a desired clock ratio value stored in a nonvolatile memory. If the clock ratio is the same as the desired clock ratio value, then the processor completes the boot of the processor. If the clock ratio is different from the desired value, then the processor writes the desired value into a latch connected to the on clock configuration input terminals of the processor and inhibits reset of the latch. The processor then generates another reset event. In this reset cycle, the processor will sense the desired clock ratio value driven onto the clock configuration input terminals by the latch and boot with the desired clock ratio.

Abstract: A fault tolerant processing system includes at least two processing planes. Each processing plane processes an input signal and generates an output signal. The system further includes plane termination logic for receiving the output signals of the processing planes to generate a non-redundant output signal. Each processing plane is provided with devices for detecting a fault in the plane, and devices for substituting, in response to detection of a fault in the plane, a signal component, referred to as control component, representing a predetermined logical state for each one of those components of the processed input signal that are affected by the detected fault. Furthermore, the plane termination logic includes devices for performing logical operations on the output signals of the planes such that, in the generation of the non-redundant output signal, unaffected signal components of a received signal override corresponding control components of another received signal.

Abstract: A memory controller used to manage the memory interface (main store interface) for processor and input and output (I/O) device access, includes a trace array used for accumulating trace data signals to be stored to main store, control logic used to determine when the array should be updated and when its contents should be stored to main store, an address register which provides the starting address of main store assigned to store trace data, an offset address register which identifies the current address to store trace data, and a space size register used to identify the amount of main store reserved to store trace data. In a first implementation, the contents of the trace array are moved to main store when the trace array becomes full. An alternative implementation provides additional control registers and logic which allow memory to be updated from the trace array when the memory interface is not busy.

Abstract: The invention relates to a method for pre-installing software program. First create a configuration file according to the demand of software programs in each destination disk drive. Then the server of a local area network creates an operating system image file and an application file package. The files are sent to the local area network station to pre-install the software. Using the method, the pre-installation of software program can be realized. Also, the user may select the programs freely without partitioning and formatting the hard disk. At the same time, the installation of software can be done in a large number of new machines automatically.

Abstract: A file control part 1 newly opens a file A in a file storage part 11 through a file accessing part 2, and secures a file data area having a certain size. An input/output control part 4 issues a request of writing into the file A to the file control part 1, and then writes data supplied from an input/output device 7 directly to a proper position of the data portion of the file A stored in a storage part 6 on the basis of information about the file A from the file control part 1. When the size of data to be written exceeds the file size previously secured, an input/output file managing part 8 requests again the file control part 1 to supplement a file data area having a certain size and makes it supplement the file data area.

Abstract: A computer system including a processor, a system memory, and a boot code storage device. The system memory is connected to the processor and is suitable for storing processor data and instructions. The boot code storage device includes an image selection indicator for indicating which of multiple boot code images are to be loaded. The computer system further includes means for initiating a boot sequence stored on the boot code storage device. The boot sequence selects from first and second boot images based upon the state of the image selection indicator and loads the selected image into the system memory in response to a boot event. In one embodiment, the image selection indicator is in an initial state until the boot code sequence successfully loads a boot image. The image selection indicator is set to a value indicative of the loaded image when one of the boot images is successfully loaded.

Abstract: A system for collecting and aggregating data from network entities for a data consuming application is described. The system includes a data collector layer to receive network flow information from the network entities and to produce records based on the information. The system also includes a flow aggregation layer fed from the data collection layer and coupled to a storage device. The flow aggregation layer receiving records produced by the data collector layer and aggregates received records. The system can also include an equipment interface layer coupled to the data collector layer and a distribution layer to obtain selected information stored in the storage device and to distribute the select information to a requesting, data consuming application.

Abstract: A remote operator interface for a network computer is provided by a pocket-sized structural enclosure which remotely mounts input and output interface devices. The input and output devices providing a remote interface to control a network computer. The pocket-sized structural enclosure provides a means for electrically coupling the input and output interface devices to the network computer. The cable or data transmission medium which electronically couples the remote operator interface to the network computer provides a communication transmission medium for the network computer system. The pocket-sized structural enclosure can be mounted to a keyboard in close proximity to the operator of a network computer.

Abstract: A computer implemented system analyzes an application state by determining entities which provide predetermined functionalities for a user determining items that depend from the determined entities, grouping entities by pruning overlapping entities and combining similar entities, and packaging the group of entities using a predetermined format. The system provides automatic relationship resolution based on a current machine state to enumerate in a deterministic manner fundamental data, metadata and dependencies necessary for correct application function. In addition, state information is stored in a persistent format to be used in a variety of applications, including installation, synchonization, backup, recovery, analysis, and repair.

Abstract: The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

Abstract: A computer system allocates processor time to multiple users. A systems operator or other administrator specifies to the computer a share of processor time for each user. A particular user's CPU usage is limited to an absolute value in a ‘dispatch driven’ multiprocessing system through the use of a monitor built into an active wait routine. The mechanism used is a list of users whose CPU resource must be limited so that their consumption does not exceed the limit value. The limit list is active wait monitored to determine when a user should be removed from the list in a low load situation and thus deliver the maximum CPU usage to the user if it is available.

Abstract: A method and computer for locally and remotely updating a BIOS using one update file that contains a local update program and a BIOS image. To locally update a client's BIOS, the system administrator can run the update file. To locally update program would then write the BIOS image to the client's computer memory thereby completing the local update. If, however, the system administrator wishes to remotely update the client's BIOS, the update file is run using an input parameter (such as a command line switch). This action causes the local update program to create a file containing the BIOS image with a header. Using this file, a remote update program writes the BIOS image to the client's computer memory.

Abstract: A programmable timer is disclosed for use in conjunction with a microcontroller circuit. The timer is used as part of a time slice arbiter in a real time operating system, which arbiter manages device routines by allocating them to distinct code time slices executable by such microcontroller. The set up of time slices, including their number, sequence, duration, etc., can be configured and optimized to achieve a desired system performance level based on characteristics of an associated system bus, devices on the bus, etc. The timer operates as a hardware controller to direct the interrupt handler to various entry points in the corresponding routines associated with interrupt based devices on a system bus.

Abstract: The present invention provides an information processing apparatus, system and method and a providing medium which allow establishment of isochronism in isochronous transactions between different environments. The information processing system includes a bridge for bridging a wire environment and a radio environment. The bridge includes a comparator which compares the count value of a cycle time register for the wire environment and the count value of another cycle time register for the radio environment with each other and outputs an error value between the count values as a cycle report packet to a node which acts as a cycle master in the radio environment. The node receives the cycle report packet transmitted thereto from the bridge and corrects the count value of a cycle time register thereof in response to contents of the cycle report packet.

Abstract: A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock.

Abstract: A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.

Abstract: A method and apparatus for synchronizing the process of updating a plurality of distributed databases is disclosed. In accordance with an embodiment of the present invention, known database management software executed by a general purpose computer connected to each of the plurality of distributed databases is modified to include the ability to limit the number of data updates which may be outstanding to the plurality of distributed databases during any particular period of time. The modified database management software monitors the number of data updates which have been sent to each of the plurality of distributed databases and only sends additional data updates to each of the plurality of distributed databases if the number of outstanding updates is less than a predetermined maximum number of outstanding data updates.

Abstract: A portable music player computational device having a digital signal processor, for processing information, and a microcontroller connected to the digital signal processor by an electronic bus, one or more semiconductor memory devices connected to the digital signal processor by a second electronic bus, where the microcontroller controls the transfer of electronic information to and from one of said memory devices, one or more input sources connected to said microcontroller, said input sources providing information for the operation of said music player, one or more output devices connected to said digital signal processor where said microcontroller controls the transfer of electronic information to one or more of said output devices.