Abstract: A DMA transfer device has stream inputting means for receiving an encoded first stream; first stream storing means for storing the first stream; a main storage unit which stores the stream of said first stream storing means; first DMA transfer executing means,for executing a first DMA transfer from said first stream storing means to said main storage unit; first DMA transfer controlling means for controlling said first DMA transfer executing means on the basis of an amount of data which are stored in said first stream storing means or a free capacity; a processing unit which produces a second stream from the first stream that is read out from said main storage unit, and which writes the second stream into said main storage unit; second stream storing means for storing the second stream of said main storage unit; second DMA transfer executing means for executing a second DMA transfer from said main storage unit to said second stream storing means; and second DMA transfer controlling means for controlli

Abstract: An enclosure module for accommodating a plurality of peripheral devices having: a computerized control unit in electrical communication with a user interface, a first and second bus with a bus expansion logic element therebetween that allows for operation of the buses as a single logical bus or as independent buses, termination circuitry for signal-appropriate bus termination, and a first and second plurality of connectors, each for electrical connection with one of the peripheral devices. The user interface to accept a first input (and can include a second, third, fourth, and so on, input) for optional manual configuration of a respective operational feature of the enclosure module, and if the input(s) is not registered, the feature can be automatically configured without the particular information provided by the input. The connectors can each have a multi-connect assembly for connection with a first, second, and third type connector.

Abstract: A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory.

Abstract: Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.

Abstract: A system for interfacing components is provided. The system includes memory, a processor, and a management module. The management module is in communication with the memory and the processor, and is configured to receive from a first component a request for an access operation comprising one of at least a write operation and a read operation, and involving a requested data address associated with a second component. The management module is also configured to determine whether data corresponding to the requested data address is missing from the memory. In addition, the management module is configured to perform the access operation, as well as to interrupt and resume the access operation when the data is missing from the memory, wherein the processor is configured to load the data from the second component to the memory while the access operation is interrupted.

Abstract: Method for maintaining an execution interval for a task requestor to a DMA. A timer is provided with two counters, one (34) to maintain the execution interval and the second (32) to track the execution time of a task in the DMA. Each task has a predetermined execution time allowance. A task acknowledge (TACK) signal enables the tracking. A task request signal (TREQ) is generated during each execution interval until the execution time allowance is completed. The length of the second counter is less than the first counter. In one embodiment, if the first counter expires before the execution time allowance is completed, a task error signal (TERR) is illustrated.

Abstract: An apparatus and method for instantly configuring a controller are provided. In one embodiment, a controller is configured by selecting an simultaneous configuration input vector, and placing at least a portion of the configuration input vector in a plurality of registers in the controller during a single clock cycle.

Abstract: There is provided a multi-functional peripheral which is easy for user to use. In the multi-functional peripheral, after a logical device control program retaining a function of a logical device to which the job is transmitted from an information processing apparatus and managing the job transmitted to the logical device is allowed to analyze the inputted job, a physical device control program retaining a function of a device engine of the peripheral and managing the job in the device engine is allowed to analyze the job.

Abstract: A device (10) for user replacement of an inoperable, first boot loader program includes a boot memory (20) including the first boot loader program beginning at a first address, a PCMCIA card (15) including a second boot loader program beginning at a second memory address, and a selector switch (12). Selector switch (12) receives the user selection of one of the first boot loader program and the second boot loader program, and generates a selection signal corresponding to the user selected boot loader program. Combinational logic (21) receiving the selection signal, enables the selected boot loader program and disabling the other boot loader program.

Abstract: A method for switching among a plurality of key functions allocated to a special key, whereby the occurrence of a phenomenon that is contrary to a user's intent can be prevented. When a key event detector 14 detects the depression of a special key, it sets a register 18 by which a request is asserted to output a make scan code that is supposed to be output when the special key is independently depressed and that is originally allocated for the special key. A key event analyzer 15 and a code generator 16 output a scan code to carry out a predetermined key function in response to the depression of a key. But if the register 18 is set when the special key is released, the key event analyzer 15 and the code generator 16 output the above described make scan code.

Abstract: A method and a system for estimating an assembling-related fraction defective coefficient of an article in the stage preceding to manufacturing, e.g. at a stage of design. Assembling operation, properties/conditions of parts to be assembled and conditions of an assembling shop having significant influence to the likelihood of occurrence of failure in assembling work are inputted as data. Estimated value of assembling-related fraction defective is arithmetically determined with high accuracy by executing an assembling-related fraction defective value estimating program on the basis of the data as inputted.

Abstract: A method and system for enhancing the efficiency of the completion of host-initiated I/O operations within a fiber channel node. The host computer component of the fiber channel node does not allocate the memory buffer for the FCP response frame received by the FC node at the completion of an I/O operation. Instead, the interface controller of the FC node processes FCP response frames in order to determine whether or not an I/O operation successfully completes. In the common case that the I/O operation successfully completes, the interface controller writes the FCP exchange ID corresponding to the I/O operation to a special location in memory which serves to invoke logic functions implemented in an ASIC that de-allocate host memory resources allocated for the I/O operation.

Abstract: A vehicle communications system, in particular for a motor vehicle, is provided having a plurality of equipment units for transmitting, receiving, acquiring and/or processing data for executing applications. The equipment units are connected to a common data bus via associated hardware interfaces. The applications are assigned flexibly controllable functions, each function being respectively assigned a software interface for exchanging data with other software interfaces and/or hardware interfaces, and the functions being executed within any desired equipment unit.

Abstract: The present invention describes an improved communication architecture for smart card systems and an improved procedure for communication of the smart card applications using protected data carriers, particularly in the case where smart cards or smart card readers cannot be used. The improved communication architecture has a common virtual smart card interface between the respective smart card applications and the modules which facilitate access to the protected data carriers (smart cards). The modules allow access to either physical smart cards, virtual software smart cards or hardware smart cards. The common virtual smart card interface means that the application is completely independent of the respective module or the respective data carrier. Alternatively, the improved communication architecture additionally contains a virtual smart card adapter which communicates over the common virtual smart card interface with the respective smart card application.

Abstract: An intelligent bus listening device, and a method which may be implemented as a computer program product, listens to SCSI commands on a first SCSI bus of a SCSI system via a listening connection to the first SCSI bus. The listening device is separately coupled via an interface to a second bus for communicating commands onto the second bus. A processor is coupled to the listening connection and to the second bus interface, the processor receiving the first commands from the first SCSI bus, converting the first commands to second commands related to the first commands, and providing the second commands to the second bus interface.

Abstract: A data output apparatus includes: a storage device in which a first storage area is formed in advance; a first receiving device for receiving a parameter set for setting a condition of the output process, and storing the received parameter set into the first storage area; a forming device for forming a second storage area in the storage device, and linking the formed second storage area with the received parameter set; a second receiving device for receiving a data set, and storing the received data set into the second storage area; a processing device for identifying the parameter set linked with the second area in which the received data set is stored, setting the condition of the output process according to the identified parameter set, and processing the received data set according to the output process whose condition is set by the identified parameter set; and an output device for outputting the processed data set.

Abstract: A system for locating and monitoring electronic devices utilizing a security system that is secretly and transparently embedded within the computer. This security system causes the client computer to periodically and conditionally call a host system to report its serial number via an encoded series of dialed numbers. A host monitoring system receives calls from various clients and determines which calls to accept and which to reject by comparing the decoded client serial numbers with a predefined and updated list of numbers corresponding to reported stolen computers. The host also concurrently obtains the caller ID of the calling client to determine the physical location of the client computer. The caller ID and the serial number are subsequently transmitted to a notifying station in order to facilitate the recovery of the stolen device. The security system remains hidden from the user, and actively resists attempts to disable it.

Abstract: A timer apparatus which can simultaneously control the operations of a plurality of timers without adjusting the operation of a counter of each timer in a software manner is provided. The same address information is added to an operation command to the counter of each timer (20, 30, 40, . . . , 90), so the operation commands to the counters are simultaneously written into registers synchronously with a clock. Thus, the timing to start or stop the operations of the counters of the timers (20, 30, 40, . . . , 90) can be made to coincide.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: A serial communication system, which can improve a communication speed even when it takes long time to perform a process in accordance with a command. A serial communication apparatus includes a first and a second microcomputer, each of which has a relationship of a master/a slave. Each of the first and the second microcomputer has a CPU, a ROM, a RAM, a communication control portion, a serial communication block and so on. A serial communication clock (SCLK) is continuously sent from the first microcomputer to the second microcomputer. The serial communication block of each of the microcomputers has a pair of exchangeable shift registers. Each of the communication control portions reads a signal (SRXD) sent from the opposite side microcomputer by 16 clocks, and performs processes based on a process command in the read signal (SRXD) during the next 16 clocks.