Abstract: Electronic devices (16, 17) can be controlled by a control unit (11), which in turn is responsive to infrared commands (33) received from a remote (12) utilized by an operator. The remote has a touch-panel display (49), on which images can be displayed. The images are part of a user interface created by a program (86) running in a personal computer (13). An operator enters into the computer an identification of the devices (16, 17) which are to be controlled, and the computer then takes predefined images and automatically customizes them for the these devices. Some of the images have a size which is less than the overall size of the display, so that when one of these images is displayed, a portion of at least one other image will also be visible.

Abstract: A Transfer Progress Alert Module and a method for optimizing processing of a data transfer load, in a data communication system is provided. The data transfer load is divided in individual data blocks. The device and method simultaneously perform pipelined operations on different individual data blocks, thus optimizing the overlap of pipelined operations. The method includes initializing the transfer by selecting a pre-defined individual data block size and determining a key for selecting and monitoring transfers with transfer addresses within a pre-determined address region. The method then continuously repeats following steps until all monitored individual data blocks from the data transfer load are processed. First, the incoming individual data blocks are transferred on a bus between a peripheral device and a memory, and the Transfer Progress Alert module is used for monitoring the individual data blocks having transfer addresses determined to belong in the pre-determined address region.

Abstract: A method and apparatus for determining position using a handheld personal computer. A cradle is disclosed that that is adapted to couple to a handheld personal computer. In one embodiment, the cradle includes projecting members that capture the handheld personal computer and hold it securely in place. The cradle includes a position determining system that is adapted to determine position. Upon coupling the cradle to a handheld personal computer, the cradle is operable to determine position. Once position is determined, the determined position is displayed on the display of the handheld personal computer. The display can include a display of a moving map and an icon indicating the current position relative to the map. All required hardware and software for storing the map database and for determining position are included within the cradle.

Abstract: A physical clock is expanded to enhance its precision. Existing instructions are capable of using the enhanced physical clock. Execution of an instruction begins, which places a value of the expanded physical clock in a physical clock field of a clock representation. The physical clock field is, however, unable to accommodate the value provided by the expanded physical clock. Thus, that value encroaches upon another predefined field of the clock representation. Completion of the instruction is therefore delayed such that the value provided by the expanded physical clock can be accommodated in the clock representation and a correct value for the another predefined field can be provided.

Abstract: A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: A processor includes a store queue and a store queue number assignment circuit. The store queue number assignment circuit assigns store queue numbers to stores, and operates upon instruction operations prior to the instruction operations reaching a point in the pipeline of the processor at which out of order instruction processing begins. Thus, store queue entries may be reserved for stores according to the program order of the stores. Additionally, in one embodiment, the store queue number identifying the youngest store represented in the store queue may be assigned to loads. In this manner, loads may determine which stores in the store queue are older or younger than the load based on relative position within the store queue. Checking for store queue hits may be qualified with the entries between the head of the store queue and the entry indicated by the load's store queue number.

Abstract: A method and apparatus for secure streaming of digital audio/visual content is disclosed. Secure streaming provides protection against unauthorized use of the digital content. Authorization and integrity checks are performed by a client or playback device on a set of data associated with digital content to be played. The set of data includes authorization and integrity information for content to be received from the source. Streamed content is received from the source by the playback device. The streamed content is intermittently checked for authorization and integrity. If the check is passed, playback continues; otherwise playback is halted.

Abstract: A system and method for managing device configuration changes. The system and method preferably comprises a management station which issues a configuration change request to a management device and waits for a reply from the managed device. The managed device receives the configuration change request from the management station and processes the change request until the configuration change request is durable on the managed device. The managed device then returns a status to the management station indicating that the configuration request is durable. The management station receives the status from the managed device and stops waiting for reply. In the meantime, the managed device continues processing the configuration change request.

Abstract: Disclosed is a codec (coder/decoder) system with shadow buffers and method of performing a Power Down/Suspend mode operation on this codec system, which allows all the codecs in the codec system to know the operating status of each other so that system crash can be prevented during a power down/suspend operation. The codec system includes two or more codecs and associated codec controllers, with each codec controller including a status data buffer and a shadow buffer; and each codec controller utilizes the status data buffer therein for registering the operating status thereof and meanwhile utilizes the shadow buffer therein for storing a copy of the operating status data stored in the status data buffer of the other codec controller. The provision of the shallow buffers allows all the codecs in the codec system to be capable of knowing the operating status of each other. This feature can help prevent system crash during power down/suspend operation.

Abstract: A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. A reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.

Abstract: Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator. After the circuit determines that the internal oscillator signal has settled, contents of non-volatile register are read to select the clock source for the circuit. Upon successful selection and clean up of system clock, the reset is removed.

Abstract: A controller (203) for coupling between a computer bus (20) and one or more units (221, 222) compatible with the bus. The controller comprises a first input (28) for receiving a first reset signal issued from the computer bus, and a second input (30) for receiving a second reset signal. The controller further comprises circuitry (26) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry (24) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.

Abstract: An interrupt routing mechanism implemented in a host chipset to eliminate the need for the general purpose I/O pins, special software and external logic devices to steer particular interrupts from a non-legacy Peripheral Component Interconnect (PCI) bus to an external interrupt controller. Such an interrupt routing mechanism may be implemented by a series of logic gates such as OR gates and AND gates for combining all interrupts from a non-legacy PCI bus to produce an output boot interrupt to an external interrupt controller, and alternatively, implemented by a series of AND gates for combining all interrupts from a non-legacy PCI bus and a switch for forwarding an output boot interrupt to an external interrupt controller in accordance with a disable bit used for the steering function.

Abstract: A computer system that includes a system ROM with at least two sets of character strings, one set in English and at least one other set in a non-English language. Generally, each set of character strings includes characters, words and phrases that are translations of corresponding character strings in the other sets. In a preferred embodiment, the system ROM includes only two sets of character strings—one English and the other non-English. The non-English set of character strings is included as part of a “language module” stored or flashed into the system ROM. The character strings preferably are used to provide information and instructions to a user during system setup. When setup is run, the computer system determines whether a valid international language module is included in the system ROM. If a valid language module is included, the user is prompted to select either English or whatever international language is provided in the language module.

Abstract: A method and apparatus which simplifies the configuration of CPEs of several models, potentially from several manufacturers. Each model may be employ a different syntax for the configuration commands. A portable system is implemented to issue commands with all such different syntaxes. The configuration parameters are retrieved from a central system and the commands are issued to each CPE to be configured. The issued commands have the syntax corresponding to the model of the configured CPE, and in some cases incorporate the retrieved parameters. The invention is particularly useful for service providers who may have the responsibility of configuring numerous CPEs of several different models.

Abstract: A method and apparatus for booting a client computer connected to a network without a boot ROM and without an operating system is provided. Instructions from a BIOS ROM are executed to load a boot code loader from a nonvolatile, read/write memory, such as a diskette or hard disk. The boot code loader executes to load a control program from the diskette, and the control program executes to load a set of programs and/or device drivers from the diskette without loading an operating system. The set of programs and/or device drivers communicate with a network server to retrieve a boot program from the network server, and the boot program executes to complete the boot process of the client, such as downloading an operating system from the server.

Abstract: The architecture of the Smart Test is described. Instead of writing a script, the Tester designs a functional model of the system to be tested, such as an application. For example, the Tester would model the functions of the system to be tested, such as a main window, a menu bar, drop-down menus, specialized windows etc. The more complete the model, the better the chance testing will cover existing function. The Tester would also define any facts that the model might need (for example, the name of the file to be opened and saved). The Tester then defines any goals or subgoals to be attained. A goal might be saving the file. Then the rules under which the model will operate are defined. One rule might be if the file (named as a fact) has its date and/or time changed, then the goal of saving the file was reached and the test will end.

Abstract: Transferring apparatus includes a main body defining a take-up position at which a rectangular glass substrate is located and a transfer position spaced apart from the take-up position. A transferring mechanism is arranged between the take-up and transfer positions and provided with a hand for supporting the substrate and transferring the substrate from the take-up position to the transfer position. Two optical sensors are provided on the hand and detect one side of the substrate located at the take-up position. A control section of the apparatus generates positional data in accordance with the detection signals from the sensors. The positional data includes an angle of the one side of the substrate to the hand and a distance between the one side and the hand. The control section controls the operation of the transferring mechanism based on the positional data so as to transfer the substrate from the take-up position and the transfer position and to position it to the transfer position.

Abstract: There is provided an address decoding circuit including (a) a first address decoder for practical use for decoding an address which is particular to an individual object, (b) a second address decoder for test use for decoding a constant address regardless of objects, and (c) a logic circuit receiving a selection signal and switching from decoding result transmitted thereto from the first address decoder to decoding result transmitted thereto from the second address decoder, and vice versa in accordance with the selection signal. The address decoding circuit selects decoding result of an address used for a test, which is particular to peripheral macros, in a test mode in accordance with the selection signal. Hence, when peripheral macros are mounted on different chips, it would be possible to use a common vector, even if an address for practical use is changed. This ensures reduction in steps of re-constructing test vector.