Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.

Abstract: A highly reliable light-emitting module including an organic EL element or a light-emitting device using a highly reliable light-emitting module including an organic EL element is provided. Alternatively, a method of manufacturing a highly reliable light-emitting module including an organic EL element, or a method of manufacturing a light-emitting device using a highly reliable light-emitting module including an organic EL element is provided. The light-emitting module has a structure in which a light-emitting element formed over a first substrate and a viscous material layer are sealed in a space between the first substrate and a second substrate which face each other, with a sealing material surrounding the light-emitting element. The viscous material layer is provided between the light-emitting element and the second substrate and includes a non-solid material and a drying agent which reacts with or adsorbs an impurity.

Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

Abstract: A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×1020 atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3.

Abstract: A method of detecting focus shift in a lithography process, a method of analyzing an error of a transferred pattern using the same, and a method of manufacturing a semiconductor device using the methods are provided. The focus shift detecting method of a lithography process comprises generating a first contour band of a mask pattern between a first focus and a second focus, generating a second contour of the mask pattern between the first focus and a third focus, and determining whether focus shift of the mask pattern occurs using an intersection of the first contour band and the second contour band.

Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.

Abstract: An embodiment of a NOR Flash device manufacturing method includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method improves the yield of the NOR Flash device.

Abstract: The method for fabricating patterns made from first material having: providing a substrate covered by a covering layer, forming a first mask by means of a self-assembled structure of block copolymers, the first mask having first patterns, making a second mask from the first mask, the second mask having a second series of patterns organized according to the first repetition pitch or an integral multiple of the first repetition pitch, the second series having less patterns than the first series, depositing and exposing a resin layer to form an intermediate mask on the first mask, the intermediate mask covering a part of the first patterns formed in the first mask and having second holes facing the first holes, etching the covering layer through the facing first and second holes to form third holes, filling the third holes with a first material to form the patterns made from first material.

Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.

Abstract: The present invention provides a method for manufacturing a flexible display device, which includes the following steps: (1) providing a flexible substrate and a number of clamps; (2) securing edges of the flexible substrate with the number of clamps; and (3) subjecting the flexible substrate to operations of exposure, development, etching, thin film deposition, annealing, and film formation, wherein in each of the operations, the clamps are adjusted in order to adjust flatness and amount of contraction of the flexible substrate and also, the clamps are adjusted to adjust angle of the flexible substrate.

Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.

Abstract: Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd?Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.

Abstract: Some embodiments include a device having a conductive material, a metal chalcogenide-containing material, and a region between the metal chalcogenide-containing material and the conductive material. The region contains a composition having a bandgap of at least about 3.5 electronvolts and a dielectric constant within a range of from about 1.8 to 25. Some embodiments include a device having a first electrode, a second electrode, and a metal chalcogenide-containing material between the first and second electrodes. The device also includes an electric-field-modifying region between the metal chalcogenide-containing material and one of the first and second electrodes. The electric-field-modifying region contains a composition having a bandgap of at least about 3.5 electronvolts having a low dielectric constant and a low conduction band offset relative to a workfunction of metal of the metal chalcogenide-containing material.

Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.

Abstract: A method for fabricating a light emitting diode (LED) die includes the steps of forming an epitaxial stack on a substrate having an n-type semiconductor layer, multiple quantum well (MQW) layers, and a p-type semiconductor layer. The method also includes the steps of forming a plurality of trenches in the n-type semiconductor layer, and forming a strap layer having conductive straps and contact areas in the trenches, forming an electrical insulator layer on the strap layer, forming an n-pad on the n-type semiconductor layer, and forming a p-pad on the p-type semiconductor layer.

Abstract: A baking apparatus for baking a wafer is provided. The baking apparatus includes a wafer chuck configured to hold the wafer, and a heating device disposed over the wafer chuck and configured to heat the wafer. The baking apparatus also includes a carrying arm configured to transport the wafer over the wafer chuck. The wafer chuck is in physical contact with the center area of the bottom surface of the wafer when the wafer is held by the wafer chuck.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: A semiconductor device includes a semiconductor layer that has a first surface and a second surface, a drift region of a first conductivity type in the semiconductor layer, a body region of a second conductivity type between the drift region and the first surface, a source region of first conductivity type, a first gate electrode, a second gate electrode with the body region interposed between the first gate electrode and the second gate electrode, first and second gate insulating films, a first field plate electrode between the second surface and the first gate electrode, a second field plate electrode between the second surface and the second gate electrode, a first region of the first conductivity type in the drift region, a second region between the first region and the body region, and a third region between the second region and the body region.