Abstract: A reflecting resin sheet provides a reflecting resin layer at the side of a light emitting diode element. The reflecting resin sheet includes a release substrate and the reflecting resin layer provided on one surface in a thickness direction of the release substrate. The reflecting resin layer is formed corresponding to the light emitting diode element so as to be capable of being in close contact with the light emitting diode element.

Abstract: A method for fabricating a flip chip light emitting diode (FCLED) die includes forming an epitaxial stack on a carrier substrate having an n-type confinement layer, a multiple quantum well (MQW) layer, and a p-type confinement layer, forming a mirror layer on the p-type confinement layer, forming an n-trench in the n-type confinement layer, forming an n-conductor layer in the n-trench on the n-type confinement layer, forming a p-metal layer on the p-type confinement layer, forming a first electrical isolator layer on the n-conductor layer and a second electrical isolator layer on the p-metal layer, forming a p-pad on the first electrical isolator layer, and forming an n-pad the second electrical isolator layer.

Abstract: A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.

Abstract: A layer system having a layer region whereby the layer region has a single-crystal silicon substrate with a front side and a back side, and whereby a textured surface is formed on the front side and the textured surface has a topography with different heights and a thin film layer of a metal oxide and/or an oxide ceramic is formed on the textured surface, whereby the thin film layer covers the textured surface.

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.

Abstract: A thin-film transistor includes an oxidic semiconductor channel, a metallic or oxidic gate, drain and source contacts and at least one barrier layer positioned between the oxidic semiconductor channel and the drain and source contacts to inhibit an exchange of oxygen between the oxidic semiconductor channel and the drain and source contacts.

Abstract: A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.

Abstract: A light emitting diode (LED) die includes a first-type semiconductor layer, a multiple quantum well (MQW) layer in electrical contact with the first-type semiconductor layer configured to emit electromagnetic radiation, and a second-type semiconductor layer in electrical contact with the multiple quantum well (MQW) layer. The light emitting diode (LED) die also includes a first pad in electrical contact with the first-type semiconductor layer, and a second pad in electrical contact with the second type semiconductor layer. The light emitting diode (LED) die also includes a strap layer having conductive straps and contact areas located in trenches in the first-type semiconductor layer.

Abstract: A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a j

Abstract: A method for manufacturing at least one optoelectronic semiconductor device includes providing a substrate and applying a number of optoelectronic semiconductor chips, which are arranged spaced apart from one another in a lateral direction, on an upper face of the substrate. At least one reflective coating is applied to the exposed areas of the substrate and the lateral surfaces of the optoelectronic semiconductor chips. Openings are introduced into the reflective coating, which completely penetrate the reflective coating. Electrically conductive material is arranged on the reflective coating and at least on some parts of the openings. Radiation penetration surfaces of the optoelectronic semiconductor chips are free of the reflective coating and the reflective coating does not laterally extend beyond the optoelectronic semiconductor chips.

Abstract: A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

Abstract: A semiconductor device has a function of storing data and includes an output terminal, a first terminal, a second terminal, a first circuit, and second circuits. The first circuit has a function of keeping the potential of the output terminal to be a high-level or low-level potential. The second circuits each include a first pass transistor and a second pass transistor which are electrically connected in series, a first memory circuit, and a second memory circuit. The first and second memory circuits each have a function of making a potential retention node in an electrically floating state. The potential retention nodes of the first and second memory circuits are electrically connected to gates of the first and second pass transistors, respectively. A transistor including an oxide semiconductor layer may be provided in the first and second memory circuits.

Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

Abstract: According to one embodiment, a releasing apparatus for separating a semiconductor substrate from a semiconductor template, the releasing apparatus having an enclosed pressure chamber having at least one gas inlet and at least one gas outlet. A top vacuum chuck for securing a released semiconductor substrate or semiconductor template in the enclosed pressure chamber. A bottom vacuum chuck for securing an attached semiconductor substrate and semiconductor template in the enclosed pressure chamber. A gap between the attached semiconductor substrate and semiconductor template and the top vacuum chuck allowing gas flowing through the gap to generate lifting forces on the attached semiconductor substrate and semiconductor template.

Abstract: A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers. The buffer layers are provided between the semiconductor layer forming a channel formation region and the source and drain electrode layers in order to particularly relieve an electric field in the vicinity of a drain edge and improve the withstand voltage of the transistor.

Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.

Abstract: A method of making a high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation pattern and a floating gate on the active region. The floating gate includes an upper portion, a lower portion having a width greater than a width of the upper portion, and a step-difference portion between the upper portion and the lower portion. A dielectric pattern is on the floating gate, and a control gate is on the dielectric pattern. The lower portion of the floating gate has a height of about 4 nm or more.