Abstract: A pellicle for an EUV lithography may include a pellicle film, a supporting structure and a handling block. The pellicle film may have a first surface for orienting opposite to a mask, and a second surface opposite to the first surface and for orienting toward the mask. The pellicle film may allow the EUV, which may pass through the mask, to penetrate the pellicle film. The supporting structure may be arranged on the second surface of the pellicle film to support the pellicle film. The handling block may be arranged on the first surface of the pellicle film. The handling block may have an opening configured to expose the pellicle film. Thus, the pellicle may be handled using the thick handling block, not the thin pellicle film, so that the thin pellicle film may not be damaged. The pellicle may protect the mask from byproducts generated in the EUV lithography process so that the mask may not be contaminated.

Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one component, disposed over and connected to the backside redistribution layer; at least one chip adjacent to the at least one component; a molding compound disposed between the at least one chip and the at least one component; a via, disposed in the molding compound and connected to the backside redistribution layer; and a front redistribution layer, disposed over the chip and the via, wherein the chip and the at least one component are connected by using the backside redistribution layer, the via and the front redistribution layer.

Abstract: A layer system having a layer region, whereby the layer region has a single-crystal silicon substrate with a front side and a back side, and whereby a textured surface is formed on the front side and the textured surface has a topography with different heights and a thin film layer of a metal oxide and/or an oxide ceramic is formed on the textured surface, whereby the thin film layer covers the textured surface only partially.

Abstract: A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the device and a spacer and a cap formed over a dummy gate line separating a source and drain of the device. The device also includes an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer.

Abstract: The present invention relates to a vacuum deposition device that includes a film forming chamber and a series of discharge circuit which evaporates the film forming materials and discharges the evaporated film forming materials toward a substrate. The discharge circuit is constituted of: evaporating parts, a manifold group; a film forming material discharge part; and a shutter member. In the film forming material discharge part, discharge openings which are communicated with manifold portions are distributed. Flow restrictions are provided in the vicinity of open ends of the discharge openings. Open areas of the flow restrictions differ from each other for the respective manifold portions. Consideration is taken such that the film forming materials which are formed into layers having similar film thicknesses are filled into the evaporating parts belonging to the same group.

Abstract: A method of forming a semiconductor device includes: providing a patterned structure comprising a silicon substrate and dielectric stacks deposited on the silicon substrate, the dielectric stacks forming trenches exposing a plurality of surface portions of the substrate within the trenches; forming one or more epitaxial buffer layers within the trenches on the exposed surface portions of the substrate; and growing a semiconductor material on the epitaxial buffer layer that is the furthest away from the substrate; wherein each of the one or more epitaxial buffer layers and the semiconductor material has less than about 3% lattice mismatch to the layer immediately beneath the one or more epitaxial buffer layer and the semiconductor material.

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.

Abstract: In various embodiments, a method for coating a workpiece is provided. The method may include drying a workpiece, the workpiece being coated with at least one oxide layer as an uppermost layer; depositing a dielectric layer over the uppermost layer of the dried workpiece; wherein the workpiece is continuously subject to a pressure which is lower than atmospheric pressure during the drying process and during the depositing process.

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip.

Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

Abstract: A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing.

Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.

Abstract: A power semiconductor device comprising: a body, a substrate and power semiconductor components arranged on and connected to the substrate. The device has electrically conductive load connection elements and an integrally formed housing which runs laterally around the components. The body has a main outer surface which runs laterally around the components and which is at least partially covered by an elastic, electrically nonconductive, integrally formed, structured sealing element which runs laterally around the components. A section of the sealing element is arranged between the housing and the main outer surface of the body. The housing and the main outer surface of the body are pressed against the sealing element, which seals off the housing from the main outer surface of the body. The invention provides a compact device whose load connection elements are reliably electrically insulated from the body and whose housing is reliably sealed off from the body.

Abstract: A method of making a semiconductor device forms anchors for one or more layers of material. The method includes depositing a first layer of material on a substrate, applying a mask over the first layer of material to mask nanoparticle-sized areas of the first material, removing portions of the first layer of material to form a first set of recesses around the nanoparticle-sized areas of the first material, depositing a second layer of material in the recesses and over the nanoparticle-sized areas so that a second set of recesses is formed in a top surface of the second layer of material, and forming a component of the semiconductor device over the second layer of material. Material of a bottom surface of the component is included in the second set of recesses.

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 ?m.

Abstract: A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the device and a spacer and a cap formed over a dummy gate line separating a source and drain of the device. The device also includes an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer.

Abstract: Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface.