Abstract: A planar MOSFET is provided on the upper surface of the N?-type semiconductor substrate in a mesa portion between the trenches. A P+-type emitter layer is provided between the trench and the planar MOSFET in the mesa portion. A P-type collector layer is provided on a lower surface of the N?-type semiconductor substrate. The planar MOSFET includes an N+-type emitter layer, an upper portion of the N?-type semiconductor substrate, a P-type base layer, and a planar gate on the foregoing with a gate insulating film interposed therebetween. The planar gate is connected to the gate trench. The P+-type emitter layer has a higher impurity concentration than the P-type base layer and has an electric potential equal to an emitter potential of the N+-type emitter layer. The N+-type emitter layer is not in contact with the trench. A trench MOSFET is not formed.

Abstract: The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a first Nth metal line of an Nth metal layer, a magnetic tunneling junction (MTJ) over first Nth metal line, and a first (N+1)th metal via of an (N+1)th metal layer, the first (N+1)th metal via being disposed over the MTJ layer. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed.

Abstract: The present invention relates to a sensor that uses a sensing mechanism having a combined static charge and a field effect transistor, the sensor including: a substrate; source and drain units formed on the substrate and separated from each other; a channel unit interposed between the source and drain units; a membrane separated from the channel unit, disposed on a top portion and displaced in response to an external signal; and a static charge member formed on a bottom surface of the membrane separately from the channel unit and generating an electric field.

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more field-effect transistor devices. A field effect transistor device includes source/drain regions disposed in an active region of a semiconductor substrate and separated from one another along a first direction by a channel region. A shallow trench isolation (STI) region, which has an upper STI surface, laterally surrounds the active region. The STI region includes trench regions, which have lower trench surfaces below the upper STI surface and which extend from opposite sides of the channel region in a second direction which intersects the first direction. A metal gate electrode extends in the second direction and has lower portions which are disposed in the trench regions and which are separated from one another by the channel region. The metal gate electrode has an upper portion bridging over the channel region to couple the lower portions to one another.

Abstract: The invention is a field-effect transistor with a channel consisting of a thin sheet of one or more atomic layers of lateral heterostructures based on hybridized graphene. The role of lateral heterostructures is to modify the energy gap in the channel so as to enable the effective operation of the transistor in all bias regions. This solution solves the problem of the missing bandgap in single-layer and multi-layer graphene, which does not allow the fabrication of transistors that can be efficiently switched off. The possibility of fabricating lateral heterostructures, with patterns of domains with different energy dispersion relations, enables the realization of field-effect transistors with additional functionalities with respect to common transistors.

Abstract: A preparation method of a glass film, a photoelectric device and a packaging method thereof, and a display device are provided, and the preparation method of a glass film includes: forming a sacrificial layer on a base substrate; forming a glass frit film on the sacrificial layer; solidifying the glass frit film; and removing the sacrificial layer, so as to obtain a glass film. The method can bring an individual glass film, which is helpful to a narrow-bezel design of a photoelectric device.

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract: A method of forming a Ti film on a substrate disposed in a chamber by introducing a processing gas containing a TiCl4 gas as a Ti source and a H2 gas as a reducing gas and by generating plasma in the chamber, includes introducing an Ar gas as a plasma generation gas into the chamber, converting the Ar gas into plasma to generate Ar ions, and acting the Ar ions on the Ti film to promote desorption of Cl from the Ti film.

Abstract: A method for forming an image-sensor device is provided. The method includes providing a first semiconductor substrate having a first surface and a second surface opposite to the first surface. The method includes forming a device layer over the first surface of the first semiconductor substrate. The method includes bonding the first semiconductor substrate to a second semiconductor substrate after the formation of the device layer. The second surface faces the second semiconductor substrate. The method includes forming a diffusion layer between the first semiconductor substrate and the second semiconductor substrate. The diffusion layer has a dopant concentration gradient that increases in a direction from the first semiconductor substrate toward the second semiconductor substrate.

Abstract: The present invention provides an organic p-n junction based ultraviolet detection device and an ultraviolet image detector using the device. The organic p-n junction based ultraviolet detection device (40) includes: an active glass substrate (42) and a packaging glass substrate (44) that are arranged and opposite to each other, a plurality of organic p-n junctions (43) arranged between the active glass substrate (42) and the packaging glass substrate (44), and a packaging material (48) arranged along a circumferential edge area of the active glass substrate (42) and the packaging glass substrate (44). The plurality of organic p-n junctions (43) is arranged in the form of an array on the active glass substrate (42).

Abstract: A MOS pass transistor includes a semiconductor layer having first conductivity, a trench isolation layer disposed in the semiconductor layer to define a first active region and a second active region, a first junction region having second conductivity, disposed in the first active region, and being in contact with a first sidewall of the trench isolation layer, a second junction region having the second conductivity, disposed in the second active region, being in contact with a second sidewall of the trench isolation layer, and being spaced apart from the first junction region, and a gate electrode disposed over the trench isolation layer. A lower portion of the gate electrode extends from a top surface of the trench isolation layer into the trench isolation layer to a predetermined depth.

Abstract: A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the semiconductor device. The isolating structure has a roughness surface at a sidewall of the isolating structure, and the roughness surface includes carbon atoms thereon.

Abstract: A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract: A method of surface functionalization for high-k deposition is provided in several embodiments. The method provides interface layer growth with low effective oxide thickness and good nucleation behavior for high-k deposition. The method includes providing a substrate that is at least substantially free of oxygen on a surface of the substrate, forming an interface layer on the surface of the substrate by exposing the surface of the substrate to one or more pulses of ozone gas, modifying the interface layer by exposing the interface layer to one or more pulses of a treatment gas containing a functional group to form a functionalized interface layer terminated with the functional group, and depositing a high-k film on the functionalized interface layer.

Abstract: A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor.

Abstract: Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A semiconductor device, such as a finFET, comprises a fin formed on a semiconductor substrate. The fin comprises a source region, a channel, and a drain region. A gate is formed around the channel. A top fin portion of the fin is annealed, such as by a hydrogen annealing process, to create one or more faceted surfaces. For example the top fin portion comprises a first faceted surface formed adjacent to a second faceted surface at an angle greater than 90 degrees relative to the second faceted surface, which results in a reduced sharpness of a corner between the first faceted surface and the second faceted surface. In this way, an electrical field near the corner is substantially uniform to electrical fields induced elsewhere within the fin.

Abstract: To form an oxide semiconductor film with a low density of localized levels. To improve electric characteristics of a semiconductor device including the oxide semiconductor. After oxygen is added to an oxide film containing In or Ga in contact with an oxide semiconductor film functioning as a channel, heat treatment is performed to make oxygen in the oxide film containing In or Ga transfer to the oxide semiconductor film functioning as a channel, so that the amount of oxygen vacancies in the oxide semiconductor film is reduced. Further, an oxide film containing In or Ga is formed, oxygen is added to the oxide film, an oxide semiconductor film is formed over the oxide film, and then heat treatment is performed.

Abstract: A method of semiconductor device fabrication including placing a substrate having a first and second features disposed thereon in a vaporizing spray deposition system. An atomizing spray head of the vaporizing spray deposition system is used to deposit a conformal polymer layer on the first and second features. The first feature having the layer of the polymer disposed thereon and having a first width. A spray trim process is performed on the first and second features having the polymer layer disposed thereon using the atomizing spray head.

Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method for etching a substrate disposed within a processing volume of a process chamber includes: (a) exposing a first layer disposed atop the substrate to a first gas comprising tungsten chloride (WClx) for a first period of time and at a first pressure, wherein x is 5 or 6; (b) purging the processing volume of the first gas using an inert gas for a second period of time; (c) exposing the substrate to a hydrogen-containing gas for a third period of time to etch the first layer after purging the processing volume of the first gas; and (d) purging the processing volume of the hydrogen-containing gas using the inert gas for a fourth period of time.