Patents Examined by Robert Beausoleil
  • Patent number: 9898527
    Abstract: A method for retrieving information includes determining, by the information retrieval management computing device, when an identified subject of interest in a received query maps to one of one or more ontology entities. An identification is made, by the information retrieval management computing device, when the identified subject of interest is one of one or more existing subjects of interest when the identified subject of interest is determined to map to one of the ontology entities. One or more filters associated with the identified subject of interest are stored by the information retrieval management computing device.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: February 20, 2018
    Assignee: Wipro Limited
    Inventor: Shishir Kumar
  • Patent number: 9201983
    Abstract: In a mobile terminal, user search information used in a Location Based Service (LBS) application is stored. A user search pattern is determined from the user search information. User search pattern information corresponding to search condition data is extracted and displayed when the search condition data are input in a search pattern mode of the LBS application.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: December 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Chan Lee, Jong-Min Lee
  • Patent number: 8433723
    Abstract: In various embodiments, multiple heterogeneous documents are processed to identify structures, such as chemical structures, contained therein, including non-embedded structures. Also described is a graphical user interface that permits a user to search for a structure or substructure within a set of electronic documents, then displays the matching structures as well as the actual pages of the documents on which the matching structures are found. Display of the actual pages allows the user to verify the matches and provides helpful context for the user.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: April 30, 2013
    Assignee: Cambridgesoft Corporation
    Inventors: Robin Y. Smith, William B. Ballard, Scott G. Flicker, Sean G. Greenhow
  • Patent number: 8060779
    Abstract: Provided are a method, system, and article of manufacture for using virtual copies in a failover and failback environment. Updates are copied from a primary first storage at the primary site to a secondary first storage at the secondary site during system operations. A second storage is maintained at at least one of the primary and secondary sites. A failover is performed from the primary site to the secondary site after a failure at the primary site. The at least one second storage is used after recovery of the primary site to synchronize the secondary site to the primary site. Only updates made to the secondary site during the failover are copied to or from the at least one second storage in response to the recovery at the primary site.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: November 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent Cameron Beardsley, Gregory Edward McBride, Robert Francis Bartfai
  • Patent number: 7539894
    Abstract: A method for accessing data in an optical disk with a drive. The drive has a memory. The optical disk has data blocks for recording data, and spare blocks for replacing defect data blocks. The method includes reading a predetermined number of spare blocks into the memory, and while reading a defect data block, checking whether a corresponding replacing spare block is stored in the memory. If so, suspending further reading of the spare block. Otherwise, reading the spare block with a predetermined number of other spare blocks into the memory to reduce further reading of spare blocks.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: May 26, 2009
    Assignee: Media Tek Inc.
    Inventor: Yuan-Ting Wu
  • Patent number: 7272754
    Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
    Type: Grant
    Filed: September 27, 2003
    Date of Patent: September 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Carl E. Love, Donald R. DeSota, Jaeheon Jeong, Russell M. Clapp
  • Patent number: 7080289
    Abstract: A microprocessor integrated circuit 104 is provided with a trace controller 120 that is responsive to trace initiating conditions to trigger commencement of tracing operation and generation of a trace data stream. In the case of a multi-word data transfer instruction LSM, the trace controller 120 is able to trigger tracing partway through that instruction such that a subset of the transfer specified by that instruction are included within the trace data stream. All transfers subsequent to the triggering transfer may be traced with those transfers subsequent to the triggering transfer being marked with place holder codes rather than more informative full trace data for the triggering transfer.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: July 18, 2006
    Assignee: ARM Limited
    Inventors: Andrew Brookfield Swaine, David James Williamson
  • Patent number: 7069478
    Abstract: A safety device for a stored-program control includes a controller which exchanges data with a stored-program control and, via a bus controller and a bus system, with the peripheral to be controlled. A memory is provided, in which safety-relevant data of the stored-program control is stored, which is accessible to the controller.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: June 27, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Reiner Wamsser, Hans-Peter Lerch, J├╝rgen Haeufgloeckner, Joachim Zeller, Gerhard Wolff
  • Patent number: 7047440
    Abstract: A dual/triple redundant computer system having in one of the preferred embodiments triple redundant I/O modules and dual redundant central processor modules (CPM) that operate in parallel executing the same application program. Each input module includes three input circuits operating in parallel. The first CPM receives input data from first and third input circuits and transmits input data of the first input circuit to the second CPM. The second CPM receives input data from second and third input circuits and transmits input data of the second input circuit to the first CPM. Each CPM then performs a two-out-of-two vote among input data produced by first, second, and third input circuits and utilizes an outvoted data as input to the application program to provide output data by execution of the application program. Each output module includes three microcontrollers operating in parallel.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 16, 2006
    Inventors: Lev R. Freydel, Nathan Ida
  • Patent number: 7032123
    Abstract: The present invention provides a method and apparatus for error recovery in a system. The apparatus comprises a directory cache adapted to store at least one entry and a control unit. The control unit is adapted to determine if at least one uncorrectable error exists in the directory cache and to place the directory cache offline in response to determining that the error is uncorrectable. The method comprises detecting an error in data stored in a storage device in the system, and determining if the detected error is correctable. The method further comprises making at least a portion of the storage device unavailable to one or more resources in the system in response to determining that the error is uncorrectable.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: April 18, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Donald Kane, Daniel P. Drogichen
  • Patent number: 6859887
    Abstract: A hierarchical method is provided for fault tolerance in a distributed computer system. A plurality of data centers is provided having a plurality of objects in each of the plurality of data centers. A local sub-protocol is used for dissemination of messages within a data center in the plurality of data centers and the local sub-protocol is activated from another data center of the plurality of data centers in a single round-trip message in the absence of faults.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: February 22, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Svend Frolund, Fernando Pedone
  • Patent number: 6728903
    Abstract: A memory test system of the present invention comprises a plurality of memory test units 90A, 90B, . . . , which test memory devices 52 to 56, a host computer (EWS) 10 which evaluates test results of the memory devices 52 to 56, and a common memory unit 12 which connects a plurality of the memory test units 90A, 90B, . . . , to the host computer (EWS) 10. The common memory unit has an interrupt controller (INT CNT) 22. In each of the memory test units 90, a slave processor (MCPU) 40 and a memory for the slave processor (MEM) 14 are provided. MCPU 40 reads memory test results and responses of local processors (RCPU) 42 to 46 which are stored in RMEMs 32 and transfers read data to SMEM 16. MCPU 40 generates an interrupt signal. When all MCPUs 40 generate interrupt signals, INT CNT 22 generates an interrupt signal INT to the EWS 10. The EWS 10 may perform several functions based on the interrupt signal INT.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: April 27, 2004
    Assignee: Advantest Corporation
    Inventor: Yoshiaki Kato
  • Patent number: 6725399
    Abstract: A method for testing computer software is described. The method is intended for operation on software which may or may not have been previously subjected to unit and integration tests, to determine if it will meet the specific requirements of an end user. The method is applicable to internally developed, contractor developed, or vendor supplied software. The method includes application in six key process areas. The six key process areas are development of a test plan, development of test cases to support the plan, development of an environment to simulate the technical environment in which the program will operate, test execution in which the tests are executed in a technical environment, compiling and analyzing the results and finally reporting the results in a form whereby the end user can determine both the feasibility of the software system for the specific requirements and any areas where additional testing or modifications are necessary.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: April 20, 2004
    Assignee: Compuware Corporation
    Inventor: John Bowman
  • Patent number: 6574749
    Abstract: In implementing a reliable distributed shared memory, a weak consistency model is modified to ensure that all vital data structures are properly replicated at all times. Write notices and their corresponding diffs are stored on a parameterizable number of nodes. Whenever a node (say the primary node) releases a lock, it sends its current vector timestamp, write notices generated during the time the lock was held and their corresponding diffs to a secondary node. The secondary nodes keeps this information separate from its own private data structures. If a node fails (detected by all nodes simultaneously through a group membership protocol) while holding a lock, then all nodes complete a lock release method, and enter a recovery operation. During this recovery operation, all nodes exchange all write notices and corresponding diffs, including backup write notices and diffs held by nodes on behalf of the failed node. After all information has been exchanged, diffs are applied and all nodes may start fresh.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: June 3, 2003
    Assignee: Nortel Networks Limited
    Inventor: Eric W. Parsons
  • Patent number: 6571355
    Abstract: A fibre channel system having a plurality of disk drives. Each one of the disk drives has a pair of redundant ports. A pair of sources of data is provided. The system includes a pair of fibre channel port by-pass cards. Each one of the cards has an input/output port connected to a corresponding one of the sources of data. Each one of the port by-pass cards provides a fiber channel loop between the input/output port thereof and a corresponding one of the pair of ports of a one, or ones, of the disk drives selectively in accordance with a control signal fed to such port by-pass card by the one of the pair of sources coupled to the input/output port thereof. Each one of the port by-pass cards has a fail-over controller and a switch, such switch being coupled to the input/output port of such one of the port by-pass cards. Each one of the fail-over controllers produces a control signal from the source coupled thereto indicating a fault in the other one of the sources.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: May 27, 2003
    Assignee: EMC Corporation
    Inventor: Thomas Linnell
  • Patent number: 6550023
    Abstract: A method and apparatus for locating defects in an on-chip memory of an integrated circuit is presented. During a memory test of on-chip memory, a known data value is written to a word in the on-chip memory, and an output data value is read back from the same addressed word in memory. A comparison of the output data value and expected data value is performed within the integrated circuit, producing a comparison result indicating which of the bit cells in the addressed word have failed. The address and comparison result are transferred external to said integrated circuit and correspond to a bitmap entry in a bitmap. The execution of a full memory test results in a complete bitmap indicating all the failed cells of the on-chip memory.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: April 15, 2003
    Assignee: Hewlett Packard Development Company, L.P.
    Inventors: Jeffery C. Brauch, Jay E. Fleischman
  • Patent number: 6546507
    Abstract: A test system for testing communications over a bus connecting electronic devices, e.g., components of a computer system is preferably embedded in the devices themselves rather than in apparatus external to them, and is responsive to digital control signals, e.g., conforming to JTAG, for scanning test data into and out of the devices. The test system has a stress injection module for injecting a set of stimulus patterns on the bus; an error identification module for identifying an error resulting from the set of stimulus patterns; a bus tuning module for adjusting one or more bus operating and signaling parameters so that testing can be performed at one or more of a number of different sets of operating and signaling parameters; a programmable control module for controlling the bus tuning module; and a presentation module for presenting a plurality of results of the testing.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: April 8, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Joseph P. Coyle, Garry M. Tobin
  • Patent number: 6543001
    Abstract: A method and apparatus for assuring data consistency in a data processing network including local and remote data storage controllers interconnected by independent communication paths. The remote storage controller or controllers normally act as a mirror for the local storage controller or controllers. If, for any reason, transfers over one of the independent communication paths is interrupted, transfers over all the independent communication paths to predefined devices in a group are suspended thereby assuring the consistency of the data at the remote storage controller or controllers. When the cause of the interruption has been corrected, the local storage controllers are able to transfer data modified since the suspension occurred to their corresponding remote storage controllers thereby to reestablish synchronism and consistency for the entire dataset.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: April 1, 2003
    Assignee: EMC Corporation
    Inventors: Douglas E. LeCrone, Yuval Ofek, Daniel A. Murphy
  • Patent number: 6530036
    Abstract: A self-healing computer storage system utilizes a proxy storage management process to service memory access requests directed to stored objects whose designated storage management process has failed. The proxy accesses the relevant parts of the stored objects fault tolerance information to service memory access requests, updating the stored object's fault tolerance information to reflect any changes. When the previously failed storage management process is restarted, it determines if the fault tolerance information for any of the objects (or parts thereof) it manages have been modified (i.e., by a proxy). If such indication is found, the restarting storage management process reconstructs its stored object data (and metadata) from the stored objects' fault tolerance information.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: March 4, 2003
    Assignee: Tricord Systems, Inc.
    Inventor: Alexander H. Frey, Jr.
  • Patent number: 6530039
    Abstract: The present invention is a system and method for testing various language versions of an application program using a single test script. An internal dictionary and/or an external dictionary are used to provide translations of command strings from one language to the specific language of the application program. The test script may then be translated at run time using the dictionaries to allow the testing program to test the application program in accordance with the language of the application program. Fuzzy match logic may be used to provide appropriate language translation of the command string. The internal dictionary may be automatically updated at run time so that it may learn language translations of unknown command strings for future runs.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: March 4, 2003
    Assignee: Microsoft Corporation
    Inventor: Feng Yang