Abstract: A system (50) for disassembling test data includes a data structure definition system (54) and a machine readable file (52). A disassembly system (56) determines a first field from the data structure definition system (54) and converts a first portion of the machine readable file (52) to a human readable format (58) according to a definition of the first field in the data structure definition system (54).

Abstract: A watchdog monitor coupled to a device bus includes in at least one executable software the ability to produce, during each frame interval, a strobe addressing a predetermined number to the monitor. The monitor responds to the interrupt and to lack of arrival of the correct predetermined number by generating a fault flag. The monitor also runs an internal counter which is reset at each interrupt signal; the count of the internal counter exceeds a threshold count if an interrupt fails to arrive. Such a timed failure results in setting of a frame fault flag. The monitor further runs an internal clock independent of the system clock. A further missing pulse detector initiates a counter at each monitor clock pulse, and raises a flag if the monitor clock counter counts a duration exceeding the monitor inter-clock-pulse interval.

Abstract: A defect area management method of an optical recording medium is disclosed. The present method is capable of managing a defective areas by storing information of defective blocks in the user block upon formatting as well as information of defective replacement blocks by extension of the user area by slipping.

Abstract: A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between the two servers, the method including: transmitting a software-generated pulse waveform from the first server to a device coupled to the first server, wherein the software-generated pulse waveform is comprises a first command corresponding to a logic level low and a second command corresponding to a logic level high; setting said device to a first state during logic level lows of said pulse waveform and to a second state during logic level highs of said pulse waveform; receiving the software-generated pulse waveform with the second server by determining when said device is in the first state and when it is in the second state; and determining when said device no longer changes from the first state to the second state.

Abstract: A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.

Abstract: In a data recovery processing, the conventional overhead, primarily, latency due to a rotational recording media is removed. Secondary, in a signal processing or in a recording and reproducing apparatus, reliability of data reproduction is improved by repeatedly processing data. These processing are achieved that input signal, i.e., raw analog signal read from the recording media is digitized to be stored in a secondary storage such as a memory or a FIFO memory. The apparatus includes a signal processing circuit to repeatedly process the stored digital signal in the secondary storage. When detecting data, operation of the circuit is efficiently controlled by a change over detector parameters, in which characteristics for the detecting performance. Resultantly, data recovery processing speed is increased and reliability of data reproduced is improved.

Abstract: A magnetic disk drive permits control to a particular one of the magnetic disk medium among a plurality of magnetic disk media on a SCSI bus and does not influence the other magnetic media, and a SCSI system employing the same. The magnetic disk drive performing exchange of data between a plurality of magnetic disk media and an external circuit through a common SCSI bus, has a plurality of reset control circuits respectively connected to the plurality of magnetic disk media by individual SCSI buses connected to the common SCSI bus, and responsive to an externally applied command data directed to own circuit, for making a reset signal on a reset signal line of the individual SCSI bus connected to the own circuit active.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: A method and apparatus in a multiprocessor data processing system for managing a plurality of processors. Monitoring for recoverable errors in a set of processors is performed. Responsive to detecting a recoverable error for a processor in the set of processors, a determination is made as to whether the recoverable error indicates a trend towards an unrecoverable error. Responsive to a determination that the recoverable error indicates a trend towards an unrecoverable error, actions are initiated to stop the processor.

Abstract: A disc storage system having a host computer interface adapted to coupled to a host computer, a disc storage medium having a disc surface and a spindle motor coupled to the disc adapted to rotate the disc. The disc includes spare data regions and permanent data regions. A transducer is positioned for reading and writing data on the disc surface. The system further includes a controller adapted to write data on the spare data regions to thereby provide a non-volatile write cache.

Abstract: A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. Various features, individually and in combination, provide a real-time trace-forward and trace-back capability with a minimal number of pins running at a minimal frequency relative to the processor.

Abstract: The present invention provides an improved fault management system and method. In one embodiment, the system includes a gateway and a management processor system. The gateway is communicatively connected to a network for receiving alarm incidents from the network. The gateway has a rule engine for (1) selecting a control object from a set of control objects based on information from the alarm incident, and (2) processing the selected control object. The management processor system has a processor for processing configuration to objects in response to the selected control object for implementing fault management objectives defined by at least one user.

Abstract: A computer system employs a first computer; a first bus switch coupled to the first computer; a data bus coupled to the first computer via the first bus switch; a second computer; a second bus switch coupled to the second computer, the data bus being coupled to the second computer through the second bus switch; and a monitor system coupled to the first computer, to the first bus switch, and to the second bus switch.

Abstract: A localized bus and/or interface condition capture module (26, 26) is incorporated at the interface (24, 34) of a bus (21) with a peripheral device (22,32), for example embedded in an interface ASIC (41), discretely to track locally bus and/or interface signal condition, and the operational state or phase of an associated peripheral device, for subsequent access, remote analysis and diagnosis.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).

Abstract: A bus extender for extending synchronous busses of limited length provides convenient access to bus cards in ATE systems. The bus extender plugs into a synchronous bus, for example, a PCI bus, and a cable carries bus signals to a remote location, where a remote card is engaged. The bus extender supports both initiator (master) and target (slave) modes of the remote card, and communicates with the remote card in the native protocol of the bus. The bus extender operates without requiring separate control from the bus. For example, the bus extender does not require its own device driver. The bus extender includes a bus snooper circuit that monitors bus transactions with the remote card and stores configuration data. The bus snooper circuit responds locally on behalf of the remote card to bus requests that require rapid responses. The bus extender further includes a state machine that copies the stored configuration data to the remote card to reset the remote card without requiring a reset of the bus.

Abstract: An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.

Abstract: A circuit connection integrity monitor detecting and isolating connection faults in data path cards is disclosed. A connection integrity monitoring method and corresponding apparatus are applicable to selector and cross-connect circuits and permit a user to monitor all points where signal traffic may be prone to misconnection.

Abstract: An information processing apparatus having a resume function which can maintain the security even when a plurality of users commonly use the apparatus. A work state at a power-off time of the apparatus is preserved together with a work state name including a user's ID in a different area in a plurality of preservation areas for resume function on a main memory for each user. When a power source is again turned on, data in the preservation area corresponding to the user's ID is used to reproduce the work state of the user at the power-off time. The work preservation areas can be provided on a file server apparatus in a network not needing battery back-up. When the information processing apparatus is used, a work state at a power-off time can be independently preserved and reproduced for each user.

Abstract: A computer system including at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints and a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, and a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto. A method of triggering a watchpoint in a computer system is also provided.