Abstract: A centralized product testing system and method for its operation are disclosed. The system has a test application server that communicates with remote users as a web-based application. Equipment testers login to the system through their web browser. They can then run tests while viewing instructions for the test and entering results in dynamically-generated web browser forms tailored to their test. Completed forms (including files generated by test equipment tied to a tester's computer) can then be uploaded to the testing system. The testing system relates the test data to the product under test and stores the data in a relational database. The test data can then be used to dynamically generate preliminary or formal test reports for compliance and other purposes. The system has many benefits. For example, because test procedures, data, and report forms are all centrally stored, they can be reliably maintained and quickly updated.

Abstract: A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

Abstract: One application of clustered computer systems is to support failover of applications and shared resources. Another is to support scalable or fault-tolerant distributed applications. The present invention utilizes a higher-level clustering mechanism (a multi-cluster) overlayed on top of multiple underlying clusters (subclusters) to extend their capabilities. In the described embodiment, subclusters supporting application and shared resource failover across a smaller number of nodes is overlayed with a multi-cluster supporting a larger number of nodes. The multi-cluster manages cluster-level communication among nodes, and the subclusters directly manage only the shared device and application resources which they are permitted to control. It is possible to move resources between nodes which reside in different subclusters. The multi-cluster layer also externalizes interfaces similar to those of the subclusters, providing application compatibility.

Abstract: Fault tolerant computer system and method requiring reduced inter-unit communications. A primary system is arranged to execute event processes in response to received commands. Each time the execution of an event process is halted, due to normal termination or an interrupt, an event generator generates an event message indicating the type of event process and the reason or timing for halting the event process. The event message is used to instruct a backup system to execute the same event process. Since the event message also specifies the reason and the timing for halting the event process, the execution of the event process can be replicated at the backup system. Thus, the primary system and the at least one backup system will be synchronized. At least one standby system may be provided for recording in an event log the sequence of event messages, and for storing an archive copy of memory contents of the primary system.

Abstract: A method for managing a computer system includes initiating a reset of the computer system from a remote location. Diagnostic software on the computer system is downloaded from the remote location.

Abstract: A circuit arrangement for the fault tolerant execution of digital computer programs includes a plurality of arithmetic logic units embodied as processor pool elements connected together so that they can each execute the program in parallel. The processor elements are connected to each other through respective data, clock and reset cross-strapping interconnect lines, and are each connected to one or more serial field buses. Each processor element includes at least one microprocessor controller for controlling the functions of the processor element in such a manner that any selected number of the processor elements can be automatically actuated at any time to simultaneously execute the program in parallel and thereby achieve a prescribed degree of redundancy in the circuit arrangement.

Abstract: Method, systems and articles of manufacture consistent with the present invention collects and displays performance data associated with executed programs. A system consistent with an implementation of the present invention collects performance analysis information from various hardware and software components of an instrumented program, and displays the performance data in a multi-dimensional format.

Abstract: A disk array apparatus includes a detection unit, delay unit, instruction issue unit, first determination unit, and assignment unit. The detection unit detects a faulty magnetic disk device delayed in response to a read instruction from a host device out of a plurality of magnetic disk devices constituting an array. The delay unit outputs a delay signal on the basis of an output from the detection unit. The instruction issue unit issues a retry instruction to the faulty magnetic disk device on the basis of the delay signal from the delay unit. The first determination unit determines in response to the retry instruction from the instruction issue unit whether the faulty magnetic disk device normally ends read processing. The assignment unit assigns a defective alternate block to the faulty magnetic disk device when the determination result of the first determination unit does not represent a normal processing end.

Abstract: A method of detecting systemic fault conditions in an intelligent electronic device is presented. The intelligent electronic device includes a microcontroller and associated memories. An algorithm (program) stored in a memory of the intelligent electronic device detects systemic fault conditions, i.e., root causes, as indicated by repeated, similar fault events.

Abstract: A PCMCIA compatible memory card having a serial communication interface is provided. The serial communication interface includes a controller, a serial transceiver, and a serial communication port. Coupled between the controller and the serial communication port, the transceiver enables the controller to send or receive data through the serial communication port. Nonvolatile memory on the card is accessible by the controller. A cable connects the serial communication port of the memory card to a serial communication port of an external host computer. The controller operates in accordance with commands received from the host computer through the serial communication port of the card for sending data read from memory of the card to the computer, writing data to memory of the card received from the computer, loading a file into memory of the card received from the computer, erasing data from memory of the card, or verifying data in memory on the card.

Abstract: Apparatus and methods for correcting protocol errors in computer networking software. More particularly, an apparatus and methods are provided for correcting a class of protocol errors that is compatible with the protocol suite being used in computer networking software. The present invention performs inband protocol correction in a single phase or in multiple phases, according to some specific embodiments.

Abstract: A bus capture circuit captures digital signals applied on respective lines of a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an external clock signal. The internal clock signal has a fixed delay relative to the external clock signal and is applied to clock a plurality of latches. Each latch latches a digital signal applied at the input terminal responsive to the internal clock signal from the clock delay circuit. The bus capture circuit further includes a plurality of signal delay circuits, each being coupled between a respective bus line and the input terminal of a respective latch. Each signal delay circuit develops a delayed digital signal having a delay time relative to the digital signal applied on the corresponding bus line, and applies the delayed digital signal to the input terminal of the corresponding latch.

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.

Abstract: According to the present invention, an apparatus and method for providing a power interlock system for computers with PCI slots is disclosed. An internal power lock apparatus according to a preferred embodiment of the present invention has a PCI detection circuit which senses the presence or absence of a PCI card or access port cover for each and every PCI slot in the computer. If any of the PCI slots do not have a PCI card installed and do not have an access cover to prevent access to the open slot, the PCI detection circuit activates the power interlock system and automatically disables the power supply.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: There is provided a memory testing apparatus provided with a failure relief analyzer, which need not initialize, prior to counting the number of failure data, failure storing memories for storing therein counted values of the number of failure data. An output altering circuit is constituted by an initialization controller 7 for outputting an initialization signal on the basis of a row failure counter address signal outputted from an RFC address formatter 33 and a column failure counter address signal outputted from a CFC address formatter 43, and data controllers 34, 44 and 84 to each of which an initialization signal outputted from the initialization controller 7 is applied. By use of the output altering circuit, respective values of data read out from each address of a row failure storing memory, each address of a column failure storing memory and each address of a total failure storing memory are outputted as “0” only when they are read out at the first time.

Abstract: A method and an apparatus for controlling the operation of a digital processing system. In one example of a method of the invention, a first status indicator is received for a first software program which is executing on the digital processing system, and it is determined whether the first software program is in a first state. In response to determining that the first software program is not in the first state, then a first predetermined function is performed. In one embodiment, several additional status indicators may be received, one for each of several software programs which are executing on the system. For each additional status indicator, it is determined whether the corresponding software program is in the first state, and if it is not in the first state, then a corresponding, predetermined function is performed, such as (for example) relaunching the corresponding software.

Abstract: A method and apparatus for efficiently testing input/output (I/O) buffer are disclosed. The I/O buffer includes multiple transistors coupled to a data output terminal. The method includes enabling a single one of the multiple transistors. A predetermined electrical voltage level is then forced upon the data output terminal, and a resultant electrical current flowing through the data output terminal (e.g., in a direction away from the I/O buffer) is measured. The measured electrical current is compared to predetermined minimum and maximum current values. A ratio of the measured electrical current to a reference current is computed, and the computed current ratio is compared to a predetermined minimum and maximum current ratio. The above steps may be repeated until each of the multiple transistors has been enabled. The drive strength of a given transistor is a measure of the amount of electrical current the transistor causes to flow through the data output terminal when enabled.

Abstract: The objective of the invention is to provide a DSP that can perform hold testing, which evaluates the halt state of the DSP core, during DSP core self-testing. DSP circuit 2 has input scheduler 8 that outputs restart signals to halt terminal HALT, which controls operation halt/restart for the of DSP core 4, when a fixed time has elapsed after operation of DSP core 4 has halted during hold testing, so the stopped DSP core 4 can be restarted. Thus, the internal state of DSP core 4 when operation restarts, can be recognized by the DSP core 4 itself, so it will be possible to implement hold testing that evaluates whether or not the DSP core 4 has correctly halted operation.

Abstract: A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge.