Patents Examined by Robert G Bachner
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Patent number: 12224200Abstract: The present disclosure provides a substrate treating apparatus. The substrate treating apparatus includes a support unit that supports a substrate, and a heating unit that irradiates a beam to the substrate and heat the substrate, and the heating unit further includes an irradiation part that irradiates the beam, and a rotation part that rotates the beam.Type: GrantFiled: August 5, 2021Date of Patent: February 11, 2025Assignee: SEMES CO., LTD.Inventors: Ji Hoon Jeong, Won-Geun Kim, Young Dae Chung, Jee Young Lee, Tae Shin Kim
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Patent number: 12225740Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.Type: GrantFiled: February 7, 2024Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Jeffrey S. Leib, Srijit Mukherjee, Vinay Bhagwat, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 12211686Abstract: Methods of forming SOI substrates are disclosed. In some embodiments, an epitaxial layer and an oxide layer are formed on a sacrificial substrate. An etch stop layer is formed in the epitaxial layer. The sacrificial substrate is bonded to a handle substrate at the oxide layer. The sacrificial substrate is removed. The epitaxial layer is partially removed until the etch stop layer is exposed.Type: GrantFiled: July 21, 2023Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Alex Usenko
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Patent number: 12205872Abstract: The invention discloses a novel packaging structure of a power semiconductor module, which mainly comprises an insulating radiating fin, a metal lead frame unit and a chip unit. The insulating radiating fin comprises an insulating layer, and an inner metal conducting layer and an outer metal conducting layer which are respectively arranged on two sides of the insulating layer; the metal lead frame unit mainly comprises a frame pin input portion, a frame pin output portion and a frame pin signal portion, the frame pin input portion is arranged on an upper side of the inner metal conducting layer in a solder welding mode, and the chip unit is welded to the middle of the inner metal conductive layer. The frame pin output portion is provided with an inner concave portion.Type: GrantFiled: May 27, 2022Date of Patent: January 21, 2025Assignee: STARPOWER SEMICONDUCTOR LTD.Inventors: Danting Feng, Junjun Fang
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Patent number: 12202082Abstract: An example welding type system includes: a welding power circuit having a control input and a welding type power output; a feedback circuit configured to provide feedback regarding the welding type power output or a weld produced using the welding type power output; and a controller connected to the feedback circuit, wherein the controller includes a parameter setting module and a process selection module, the process selection module configured to automatically select a welding process from a plurality of welding processes based on the feedback from the feedback circuit or one or more welding parameters set by the parameter setting module.Type: GrantFiled: February 2, 2021Date of Patent: January 21, 2025Assignee: Illinois Tool Works Inc.Inventors: Bruce P. Albrecht, Robert R. Davidson
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Patent number: 12199057Abstract: A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.Type: GrantFiled: July 31, 2024Date of Patent: January 14, 2025Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Yusuke Ito, Takahiro Maeda, Akira Kimura, Tsubasa Inoue, Masahiro Mitsuda
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Patent number: 12198983Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.Type: GrantFiled: October 26, 2020Date of Patent: January 14, 2025Assignee: SoitecInventors: Ionut Radu, Hugo Biard, Christophe Maleville, Eric Guiot, Didier Landru
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Patent number: 12194574Abstract: A system and method generates a short circuit arc welding waveform output, having a pinch phase with a break point and a necking threshold, between a welding electrode and a work piece during a short circuit arc welding process. A necking threshold energy and a break point energy of the short circuit arc welding waveform output are monitored during the short circuit arc welding process, and a running average of the necking threshold energy is generated. An actual pinch energy relationship value is calculated based on the running average of the necking threshold energy and the break point energy, and is compared to a previously specified pinch energy relationship value. The break point energy of the short circuit arc welding waveform output is adjusted in response to the comparison to maintain the actual pinch energy relationship value to be at the specified pinch energy relationship value.Type: GrantFiled: September 2, 2021Date of Patent: January 14, 2025Assignee: LINCOLN GLOBAL, INC.Inventors: Daniel P. Fleming, Judah B. Henry
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Patent number: 12183863Abstract: The present disclosure discloses a drive backplane, a manufacturing method thereof and a display panel. The drive backplane includes: a base substrate; a first conductive layer, located on the base substrate; a first flat layer, located in a region, other than a pattern of the first conductive layer, on the base substrate; a second flat layer, located on a side, facing away from the base substrate, of the first conductive layer and the first flat layer, where the second flat layer includes a plurality of first via holes; and a second conductive layer, located on a side, facing away from the base substrate, of the second flat layer, where a pattern of the second conductive layer is electrically connected with the pattern of the first conductive layer through the first via holes.Type: GrantFiled: August 20, 2021Date of Patent: December 31, 2024Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Haifeng Hu, Ting Zeng, Zhanqi Xu, Jian Yang, Liuyue Yin
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Patent number: 12172851Abstract: Disclosed is a cutting system, which includes: a feed unit to supply a plurality of pre-loaded trays in sequential order; a loading unit to load the tray supplied from the feed unit with a subject to be processed (“subject”); a storage unit to load the plurality of trays loaded with the subjects in multiple stages to temporally store the same, followed by sequentially re-supplying the subjects in accordance with a change in formation of the product; a machining unit to cut the subject delivered from the storage unit with laser so as to form the product; and a recovery unit that measures a weight of the product formed in the machining unit and recovers the same. According to the present invention as described above, a cutting process to cut the subject so as to form a product and a weight-measuring process to measure a weight of the formed product may be successively executed in a single line, thereby enhancing productivity of the product.Type: GrantFiled: July 27, 2021Date of Patent: December 24, 2024Assignee: NPS CO.,LTDInventor: Seong Ho Bae
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Patent number: 12176439Abstract: A semiconductor device with small fluctuations in transistor characteristics can be provided. The semiconductor device includes a first oxide, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide and between the second oxide and the third oxide, a first insulator over the fourth oxide, and a third conductor over the first insulator. The first oxide includes a groove in a region not overlapping with the second oxide and the third oxide. The first oxide includes a first layered crystal substantially parallel to the surface where the first oxide is formed. In the groove, the fourth oxide includes a second layered crystal substantially parallel to the surface where the first oxide is formed. A concentration of aluminum atoms at an interface between the first oxide and the fourth oxide and in the vicinity of the interface is less than or equal to 5.0 atomic %.Type: GrantFiled: February 13, 2020Date of Patent: December 24, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Erika Takahashi, Tsutomu Murakawa, Shinya Sasagawa, Katsuaki Tochibayashi
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Patent number: 12176271Abstract: Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.Type: GrantFiled: October 27, 2023Date of Patent: December 24, 2024Assignee: ROHM CO., LTD.Inventors: Atsushi Yamaguchi, Hiroyuki Sakairi, Takukazu Otsuka
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Patent number: 12170201Abstract: A method for preparing a semiconductor structure, and a semiconductor structure are provided. In a prepared first pattern structure, a thickness of a first insulating layer is equal to a thickness of a second insulating layer, and a thickness of a third insulating layer is equal to a thickness of a fourth insulating layer.Type: GrantFiled: September 30, 2021Date of Patent: December 17, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Qiang Wan, Tao Liu, Sen Li
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Patent number: 12170227Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.Type: GrantFiled: September 26, 2023Date of Patent: December 17, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chien-Te Tu, Hsin-Cheng Lin, Chee-Wee Liu
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Patent number: 12166062Abstract: The present technology relates to a solid-state imaging device, a driving method therefor, and an electronic apparatus capable of acquiring a signal to detect phase difference and a signal to generate a high dynamic range image at the same time. The solid-state imaging device includes a pixel array unit in which a plurality of pixels that receives light of a same color is arranged under one on-chip lens. The plurality of pixels uses at least one pixel transistor in a sharing manner, some pixels out of the plurality of pixels are set to have a first exposure time, and other pixels are set to have a second exposure time shorter than the first exposure time. The present technology can be applied to, for example, a solid-state imaging device or the like.Type: GrantFiled: October 13, 2023Date of Patent: December 10, 2024Assignee: Sony Group CorporationInventors: Akira Tanaka, Shohei Shimada
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Patent number: 12154885Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.Type: GrantFiled: August 15, 2023Date of Patent: November 26, 2024Assignee: EPISTAR CORPORATIONInventors: Min-Hsun Hsieh, Shih-An Liao, Ying-Yang Su, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
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Patent number: 12151321Abstract: A wire feeder includes an exterior housing and in interior housing that creates an interstitial spaced that is disposed between the exterior and interior housing. This housing structure reduces weight of the wire feeder while maintaining the structural rigidness required of a wire feeder. This housing structure also promotes improved cooling features for the wire feeder and the components disposed within the wire feeder. The exterior housing may be constructed of a materials that reduces the likelihood of being damaged. The wire feeder may be further equipped with a strain relief device for the incoming supply cables, and an interchangeable cable connector. The wire feeder may also be equipped with removable wire guides for the wire feeder mechanism that are toolless. The wire feeder may be equipped with accessory storage and attachment features, as well as a cost reduced repositionable control panel.Type: GrantFiled: April 29, 2021Date of Patent: November 26, 2024Assignee: ESAB ABInventors: Jeroen Dekker, Mattias Glädt, Arne Lagerkvist, Fredrik Stjernlöf, Johan Johansson
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Patent number: 12151306Abstract: A device and a method for beam shaping and beam movement during laser material processing with a laser beam source (1) for continuously emitting a laser beam (2), a first optical deflection element (3), a second optical deflection element (4), and an optical focusing element (5) arranged between the second optical deflection element (4) and a workpiece surface (7) to be processed. The second optical deflection element (4) is configured to displace a point of incidence of the laser beam (2) on the workpiece surface (7), and the first optical deflection element (3) is configured to alter a position of a focal plane of the laser beam (2) relative to the workpiece surface (7) by means of a translational movement and/or to change an intensity distribution within a beam cross section of the laser beam.Type: GrantFiled: November 25, 2019Date of Patent: November 26, 2024Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Andreas Wetzig, Achim Mahrle, Patrick Herwig, Jan Hauptmann, Ramona Eberhardt, Paul Boettner
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Patent number: 12154968Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode a first strain-compensating layer, and a first protection layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is disposed between the source and drain electrodes. The first strain-compensating layer is disposed above the second nitride-based semiconductor layer and between the drain and gate electrodes.Type: GrantFiled: February 25, 2021Date of Patent: November 26, 2024Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Ronghui Hao, Chuan He, King Yuen Wong
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Patent number: 12145840Abstract: A MEMS sensor. The MEMS sensor includes a deflectably situated functional layer, a conversion device for converting a deflection of the functional layer into an electrical signal, the conversion device including at least one electrical element, the at least one electrical element being at least partially electrically connected to a first area, and the first area being at least partially electrically connected to a second area, and the first and second areas and/or the first area and the at least one electrical element being electrically operable in a reverse direction and a forward direction, and a control unit, the control unit being designed to at least partially operate the at least one electrical element and the first area and/or the first area and the second area in the forward direction to provide thermal energy.Type: GrantFiled: January 20, 2020Date of Patent: November 19, 2024Assignee: ROBERT BOSCH GMBHInventors: Arne Dannenberg, Mike Schwarz