Patents Examined by Robert G Bachner
  • Patent number: 11063010
    Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Yen-Jui Chu, Jin-Neng Wu, Hsin-Hung Chou, Chun-Hung Lin
  • Patent number: 11056523
    Abstract: Optical sensors including a light-impeding pattern are provided. The optical sensors may include a plurality of photoelectric conversion regions, a plurality of lenses on the plurality of photoelectric conversion regions, and a light-impeding layer extending between the plurality of photoelectric conversion regions and the plurality of lenses. The light-impeding layer may include an opening between a first one of the plurality of photoelectric conversion regions and a first one of the plurality of lenses. The optical sensors may be configured to be assembled with a display panel such that the plurality of lenses are disposed between the light-impeding layer and the display panel.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 6, 2021
    Inventors: Jonghoon Park, Bumsuk Kim, Jung-Saeng Kim, Min Jang, Taesub Jung, Hyukjin Jung, Dongmin Keum, Changrok Moon
  • Patent number: 11049799
    Abstract: A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 29, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fong Lin, Shin-Cheng Lin, Cheng-Wei Chou, Yu-Chieh Chou
  • Patent number: 11049803
    Abstract: A semiconductor module includes: an insulating substrate; a metal pattern provided on the insulating substrate; a solder resist provided on the metal pattern; a semiconductor chip mounted on the metal pattern at an opening portion of the solder resist; and a sealing material sealing the metal pattern, the solder resist and the semiconductor chip, wherein a suction area surrounded by a groove is provided in a portion of the solder resist.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 29, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Matsumoto, Yukimasa Hayashida
  • Patent number: 11048777
    Abstract: Techniques for synthesizing security exploits via self-amplifying deep learning are provided. In one example, a computer-implemented method can comprise generating, by a system operatively coupled to a processor, a probabilistic model based on an evaluation of one or more first payloads included in a first group of payloads. The computer implemented method can also comprise determining, by the system, based on the probabilistic model, that at least one first payload from the first group of payloads is invalid. Additionally, the computer implemented method can comprise, generating, by the system, a second group of payloads based on removing the at least one invalid first payload from the first group of payloads.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Supriyo Chakraborty, Omer Tripp
  • Patent number: 11049878
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Patent number: 11037060
    Abstract: Sequence data, such as time series data is analyzed using neural networks, for example, recurrent neural networks. The sequence data is obtained from a source. For example, a sequence data may represent time series data obtained from a sensor. As another example, the sequence of data may represent a sequence of user interactions performed by a user with an online system. The sequences of data are provided as input to a neural network. A feature vector representation of each input sequence data is extracted from the neural network. The feature vector representation is used for clustering the sequence data. Salient features of clusters of sequence data are determined. The salient features of clusters of sequence data are provided for display via a user interface.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 15, 2021
    Assignee: Arimo, LLC
    Inventors: Christopher T. Nguyen, Nhan Vu Lam Chi, Binh Han, Anh H. Trinh, Mohammad Saffar
  • Patent number: 11038096
    Abstract: Stack assembly having electro-acoustic device. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 15, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hardik Bhupendra Modi, Adarsh Karan Jaiswal, Anil K. Agarwal, Engin Ibrahim Pehlivanoglu
  • Patent number: 11037972
    Abstract: The present disclosure relates to an imaging device, an imaging apparatus, and an electronic device capable of light-shielding a charge accumulation unit at low cost, while maintaining a charge transfer path from a photodiode to a charge accumulation unit. A depth of a trench that forms a trench buried film having a light-shielding characteristic for preventing color mixture of the photodiodes is adjusted according to a contact amount of a reactive gas by adjusting, among the shapes of a photomask pattern, a width of the trench through which the reactive gas flows or the number of intersections of the trenches at a portion in which the trench buried film is formed. As a result, the trench buried films having a plurality of depths can be formed by a single dry etching with one mask pattern, and the manufacturing cost is reduced. Application to an imaging device is possible.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 15, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Koji Neya
  • Patent number: 11038106
    Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Carl Radens, Kangguo Cheng, Juntao Li, Ruilong Xie
  • Patent number: 11037756
    Abstract: Methods, tools and systems for patterning of substrates using charged particle beams without photomasks, without a resist layer, using multiple different processes (different chemistry processes and/or different ones of material deposition, removal and/or modification) in the same vacuum space, wherein said processes are performed independently (without cross-interference) and simultaneously. As a result, the number of process steps can be reduced and some lithography steps can be eliminated, reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Also, because such processes are resist-less, layer-to-layer registration and other column control processes can be performed by imaging previous-layer features local to (or in contact with) features to be written in a next layer as designated by the design layout database.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 15, 2021
    Inventors: David K. Lam, Kevin M. Monahan, Michael C. Smayling, Theodore A. Prescop
  • Patent number: 11037048
    Abstract: An automated conversation is facilitated between a user and a virtual agent. A system receives an input message from the user and analyzes an intent of the input message. Based on the intent of the input message, the system generates a plurality of bids for responding to the input message, and assigns an intent confidence score to each bid from the plurality of bids based on a confidence level of each bid from the plurality of bids. The system determines a winning bid from the plurality of bids based on the intent confidence score associated with each bid from the plurality of bids, and generates a response based on the winning bid.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 15, 2021
    Assignee: MOVEWORKS, INC.
    Inventors: Chang Liu, Ye Wang, Jing Chen, Jiang Chen
  • Patent number: 11031472
    Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 8, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Almern Losee, Reza Ghandi, Alexander Viktorovich Bolotnikov
  • Patent number: 11027360
    Abstract: A bonded body includes a first metal piece, a second metal piece, and a spacer. The first metal piece has a first surface and a protrusion protruding on the first surface. The second metal piece has a second surface, and the second surface of the second metal piece is bonded to the first surface of the first metal piece at the protrusion. The spacer has an electrically insulating property. The spacer is provided on the first surface of the first metal piece, and located between the first metal piece and the second metal piece. The first metal piece and the second metal piece are arranged to face each other such that a portion of the first surface of the first metal piece outside of the spacer is exposed from the second metal piece.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 8, 2021
    Assignee: DENSO CORPORATION
    Inventor: Kazuaki Mawatari
  • Patent number: 11031483
    Abstract: A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 11030545
    Abstract: Methods, systems, and devices for determining device associations are described. Some database systems may store information related to device characteristics. Each of these devices may be operated by one or more users, and each user may operate one or more devices. In some cases, information about users may be more valuable than information about devices. As such, a system may determine probable associations between devices, where an association can correspond to operation by a same user. To determine device associations, the system may perform a machine-learning process (e.g., using probabilistic soft logic (PSL) and a hinge-loss Markov Random Field (HL-MRF) model) on input device characteristics and connection information to generate a probability density function. The probability density function may indicate associations between devices within the system.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: June 8, 2021
    Assignee: salesforce.com, inc.
    Inventors: Yacov Salomon, Jonathan Budd
  • Patent number: 11029279
    Abstract: A method of detecting cells is provided. The method includes the following steps. A sensor device including a base and at least one response electrode is provided, wherein the response electrode is spaced apart from the base with respect to a gate end of the base. A test solution containing a target cell is placed on the response electrode, a first pulse voltage is applied to the response electrode, and a first detection current generated from the base is measured. A membrane potential of the target cell is changed, a second pulse voltage is applied to the response electrode, and a second detection current generated from the base is measured, wherein a sign of the first detection current and a sign of the second detection current are opposite.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 8, 2021
    Assignee: National Tsing Hua University
    Inventors: Yu-Lin Wang, Anil Kumar Pulikkathodi
  • Patent number: 11024539
    Abstract: A method for fabricating a semiconductor device includes forming at least one sacrificial via within at least one self-aligned via hole of a base structure, forming a region having a misalignment relative to the at least one sacrificial via by cut patterning, and forming a cut cavity having a geometry for minimizing effects of the misalignment by protecting at least one self-aligned via due to the misalignment.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Chih-Chao Yang, Jing Guo, Kangguo Cheng
  • Patent number: 11024590
    Abstract: Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 1, 2021
    Assignee: Seagate Technology LLC
    Inventors: Abhishek Nagaraj Laguvaram, Vinod Arjun Huddar
  • Patent number: 11018189
    Abstract: A storage apparatus includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: May 25, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Seiji Nonoguchi, Katsuhisa Aratani, Kazuhiro Ohba