Abstract: A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.

Abstract: A light detection device includes: a back-illuminated light receiving element; a circuit element; a connection member; an underfill; and a light shielding mask. The light shielding mask includes a frame having an opening and a light shielding layer formed on an inner surface of the opening. A first opening edge on the side of the circuit element in the opening is located at the outside of an outer edge of the light receiving element. A second opening edge opposite to the circuit element in the opening is located at the inside of the outer edge of the light receiving element. The opening is narrowed from the first opening edge toward the second opening edge. A width of the frame increases from the first opening edge toward the second opening edge. The underfill reaches a gap between the light receiving element and the light shielding layer.

Abstract: A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.

Abstract: A butt-welding device and a method for butt welding workpieces, especially for double-upset resistance-pressure butt-welding of workpieces, particularly wires, strands and profiles, has first and second clamping members for receiving the ends of the workpieces that are to be joined. At least one clamping means can be moved between a starting position and a welding position. At least one deburring tool is provided for deburring the welded workpiece ends. In addition, at least one sensor is provided to determine the geometric dimensions of the workpieces that are to be joined, especially the diameter, the width or the height in the joining plane or substantially parallel thereto, wherein a control unit controls the movement of the clamping members and/or of the deburring tool as a function of the geometric dimension.

Abstract: The present technology relates to a solid-state imaging device, a driving method therefor, and an electronic apparatus capable of acquiring a signal to detect phase difference and a signal to generate a high dynamic range image at the same time. The solid-state imaging device includes a pixel array unit in which a plurality of pixels that receives light of a same color is arranged under one on-chip lens. The plurality of pixels uses at least one pixel transistor in a sharing manner, some pixels out of the plurality of pixels are set to have a first exposure time, and other pixels are set to have a second exposure time shorter than the first exposure time. The present technology can be applied to, for example, a solid-state imaging device or the like.

Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament.

Abstract: A method for changing a set point of a system where period of a dominant resonance of the system is determined, a change profile for the set point change is processed; a time period for the set point change based on the period of the dominant resonance in order to minimize excitation of the dominant resonance is also processed; and the set point change is actioned according to the processed change profile and the time period.

Abstract: A semiconductor memory device includes a substrate including a first to a fourth region, first conductive layers from the first to second region, second conductive layers from the fourth to second region, third conductive layers from the first to third region, fourth conductive layers from the fourth to third region, a first semiconductor column opposed to the first and third conductive layers in the first region, a second semiconductor column opposed to the second and fourth conductive layers in the fourth region, first and second contacts connected to the first and the second conductive layers in the second region, third and fourth contacts connected to the third and fourth conductive layers in the third region, first wirings connected to the first and second contacts in the second region, and second wirings connected to the third and fourth contacts in the third region.

Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

Abstract: A capacitor may include a lower electrode, a dielectric layer structure on the lower electrode, and an upper electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers. The insert layer structure may include a plurality of zirconium oxide layers and at least one insert layer. The insert layer may be between ones of the plurality of zirconium oxide layers. The capacitor may have a high capacitance and low leakage currents.

Abstract: A semiconductor module includes: a semiconductor element having a first main electrode and a second main electrode; a first conductive member and a second conductive member connected to the first main electrode and the second main electrode, respectively, and placed to sandwich the semiconductor element; and a main terminal including a first main terminal continuous from the first conductive member and a second main terminal continuous from the second conductive member. The main terminal has a facing portion, a non-facing portion, a first connection portion, and a second connection portion. In a width direction, a formation position of the second connection portion overlaps with a formation position of the first connection portion.

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

Abstract: Methods and systems for detection of an endpoint of a substrate process are provided. A set of machine learning models are trained to provide a metrology measurement value associated with a particular type of metrology measurement for a substrate based on spectral data collected for the substrate. A respective machine learning model is selected to be applied to future spectral data collected during a future substrate process for a future substrate in view of a performance rating associated with the particular type of metrology measurement. Current spectral data is collected during a current process for a current substrate and provided as input to the respective machine learning model. An indication of a respective metrology measurement value corresponding to the current substrate is extracted from one or more outputs of the trained machine learning model.

Abstract: An imaging device includes at least one first pixel electrode, at least one second pixel electrode, a photoelectric converter continuously covering upper surfaces of the at least one first pixel electrode and the at least one second pixel electrode, a first counter electrode facing the at least one first pixel electrode, a second counter electrode facing the at least one second pixel electrode, and a sealing layer continuously covering upper surfaces of the first and second counter electrodes. In a plan view, a first portion of an upper surface of the photoelectric converter in an interelectrode region between the first counter electrode and the second counter electrode is more depressed than a second portion of the upper surface of the photoelectric converter in an overlap region overlapping the first counter electrode or the second counter electrode. The sealing layer is in contact with the photoelectric converter in the interelectrode region.

Abstract: A resistance spot welding electrode cap contains a groove at the center of the welding contact interface. During welding, because of the groove, the area of contact between the electrode cap and a metal workpiece to be soldered is reduced. In the initial stage, the overall heat generation is concentrated on the outer ring of the weld point and heat dissipation becomes slower, helping a weld nugget to form from the outside to the inside. Due to the presence of the groove, the metal workpiece expands toward the groove at the center of the electrode, thereby increasing the size of the weld nugget and reducing splash and deformation. In comparison with conventional electrode caps, the welding current required to form weld points of the same size is lower, saving on electricity costs, and weld points obtained using the same current have higher strength and stability with fewer welding defects.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

Abstract: A semiconductor device according to the present invention includes: a circuit board; a semiconductor element having a main electrode; a metal frame; and a metal plate having a flat plate shape, the metal plate being disposed between the metal frame and the main electrode, wherein the metal plate and a conductive bonding material, form a stress relaxation structure which relaxes a stress applied to metal plate and the conductive bonding material, disposed between the metal frame and the semiconductor element, and the stress relaxation structure is configured such that a thickness of the metal plate is smaller than a thickness of the metal frame, and at least one convex portion is formed on the metal plate at a position which corresponds to the main electrode. The semiconductor device according to the present invention can relax a stress applied to a conductive bonding material between a semiconductor element and a metal frame even when a relatively thick metal frame is used.