Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that avow improved reliability under high current operation.

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

Abstract: The invention provides a graphical user interface implemented on a computer including an information area for displaying to a user at the computer inspection status information in connection with one or more components of a linear asset infrastructure. The graphical user interface also includes a control component operable by the user at the computer to cause the graphical user interface to display additional information on the one or more components of the linear asset infrastructure.

Abstract: A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.

Abstract: A learning system, a walking training system, a method, a program, and a trained model for performing walking training at appropriate setting parameters are provided. A learning system according to an embodiment includes: a data acquisition unit configured to acquire rehabilitation data from a walking training system including an actuator configured to assist a walking motion of a trainee and a control unit configured to control the actuator in accordance with a setting parameter; a data generation unit configured to generate the rehabilitation data including detection data and the setting parameter as learning data; and a learning unit configured to perform machine learning using the learning data, thereby generating a learning model that receives the detection data and outputs a recommended value of the setting parameter.

Abstract: Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

Abstract: A packaged semiconductor device includes a semiconductor die having a top side including a semiconductor surface layer having circuitry configured for a function coupled to bond pads, and a bottom side. A leadframe includes a die pad and leads or lead terminals on at least two sides of the die pad. At least one non-through hole for delamination prevention is in at least one of the die pad and the lead or the lead terminals. The semiconductor die is mounted by a die attach material with the bottom side down on the die pad. A mold compound provides encapsulation for the package semiconductor device except for at least a bottom side of the lead terminals or sidewalls of the package for the leads. The non-through hole is a filled hole filled with either the die attach material or the mold compound.

Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.

Abstract: Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium-and-nitrogen-containing region.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. A resistive memory element has a first electrode, a second electrode partially embedded in the first electrode, a third electrode, and a switching layer positioned between the first electrode and the third electrode. The second electrode includes a tip positioned in the first electrode adjacent to the switching layer and a sidewall that tapers to the tip.

Abstract: A photosensitive device including a microlens substrate, a photosensitive element substrate, and an optical glue is provided. The microlens substrate includes a first substrate and microlenses. The first substrate has a first side and a second side opposite to the first side. The microlenses are located on the first side of the first substrate. The photosensitive element substrate includes a second substrate, active components, first electrodes, a second electrode, and an organic photosensitive material layer. The second substrate has a third side and a fourth side opposite to the third side. The second side of the first substrate faces the third side of the second substrate. The active components are located on the fourth side of the second substrate. The first electrodes are respectively electrically connected to the active components. The organic photosensitive material layer is located between the first electrodes and the second electrode.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide buried contacts in the fin-to-fin space of vertical transport field effect transistors (VFETs) that connect the bottom S/D of the transistors to a buried power rail. In a non-limiting embodiment of the invention, a buried power rail is encapsulated in a buried oxide layer of a first wafer. First and second semiconductor fins are formed on a second wafer. The first wafer to the second wafer and a surface of the buried power rail in a fin-to-fin space is exposed. A buried via is formed on the exposed surface of the buried power rail. The buried via electrically couples the buried power rail to a bottom source or drain region of the first semiconductor fin.

Abstract: A molded photosensitive assembly of a camera module includes at least one supporting member formed by a first substance, at least one photosensitive element, at least one circuit board, at least one set of wires electrically connecting the photosensitive element to the circuit board, and at least one molded base. Two ends of each of the wires are respectively connected to a chip connector of the photosensitive element and a circuit connector of the circuit board. The molded base is formed by a second substance and comprises a molded body and has at least one light window, wherein the photosensitive element and the wires are protected by a supporting member which is provided for avoiding an upper mold of a molding-die pressing on the wires during the molding process.

Abstract: A method for forming a memory includes: providing a substrate, a plurality of discrete bit line structures being located on the substrate, and an area surrounded by the adjacent bit line structures and the substrate and having a central axis; forming, on the substrate, a first conductive film filling an area between the adjacent bit line structures; etching the first conductive film by a first etching process to form a first conductive layer; forming a second conductive film on the top surface of the first conductive layer; and etching the second conductive film and the first conductive layer by a second etching process, the remaining second conductive film and the first conductive layer forming a capacitive contact window.

Abstract: A semiconductor structure includes a substrate having first and second bottom electrodes disposed thereon. The first bottom electrode includes a first sidewall and a second sidewall. An upper portion of the first sidewall comprises a slope profile. The second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall is opposite to the third sidewall. An upper supporting layer extends laterally between and the first bottom electrode and the second bottom electrode and directly contacts the second sidewall and the third sidewall. A lower end of the slope profile is not lower than a lower surface of the upper supporting layer. A cavity extends laterally between the substrate and the upper supporting layer. A capacitor dielectric layer is formed along the first bottom electrode and the second bottom electrode. A conductive material is formed on the capacitor dielectric layer and fills the cavity.

Abstract: A manufacturing method of a semiconductor device includes sealing a metal plate on which a semiconductor chip and a control IC are mounted by injecting molding resin raw material into a cavity from an inlet, filling the cavity with the molding resin raw material, and discharging excessive molding resin raw material from an outlet. In the case of the semiconductor device manufactured in this way, at least, generation of voids is reduced in an area around the semiconductor chip and the control IC. Thus, occurrence of an electrical discharge in the semiconductor device is reduced, and deterioration of the reliability of the semiconductor device is prevented.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: The embodiments disclosed in this document are directed to an AI-enabled microgrid and DER planning platform that uses AI methods and takes into account cost calculations, emission calculations, technology investments and operation. In an embodiment, the computing platform is deployed on a network (cloud computing platform) that can be accessed by a variety of stakeholders (e.g., investors, technology vendors, energy providers, regulatory authorities). In an embodiment, the planning platform implements machine learning (e.g., neural networks) to estimate various planning parameters, where the neural networks are trained on observed data from real-world microgrid/minigrid and DER projects.

Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.

Abstract: Provided are a III-nitride semiconductor light-emitting device that can reduce change in the light output power with time and has more excellent light output power, and a method of producing the same. A III-nitride semiconductor light-emitting device 100 has an emission wavelength of 200 nm to 350 nm, and includes an n-type layer 30, a light emitting layer 40, an electron blocking layer 60, and a p-type contact layer 70 in this order. The electron blocking layer 60 has a co-doped region layer 60c, the p-type contact layer 60 is made of p-type AlxGa1-xN (0?x?0.1), and the p-type contact layer 60 has a thickness of 300 nm or more.