Abstract: Behavioral verification of user identity includes building a deep neural network for keystroke-based behavioral verification of user identity. The building includes receiving recorded keystroke events, each such recorded keystroke event including (i) an indication of whether the recorded keystroke event is a key press or a key release, (ii) a key identifier of the respective key pressed or released, and (iii) a timestamp of the recorded keystroke event. The building further includes performing pre-processing of the recorded keystroke events to provide data structures representing sequential key events for processing by a deep neural network to extract local patterns, and training the deep neural network using the data structures. The method also includes providing the trained deep neural network for keystroke-based behavioral verification of user identity based on determinate vectors output from the trained deep neural network.

Abstract: Disclosed are substrates having an electronic component, including a frame having a through hole, the electronic component disposed in the through hole, a first wiring portion formed on a surface of the frame and the electronic component, a first layer formed on the first wiring portion, and a second wiring portion formed on the first layer, and the second wiring portion including an antenna layer.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: An integrated circuit structure comprises a dielectric layer on a substrate. An open structure is in the dielectric layer, and a void-free metal-alloy interconnect is formed in the open structure, wherein the void-free metal-alloy interconnect comprise a metal-alloy comprising a combination of two or more metallic elements excluding any mixing effects of a seed layer or liner deposited in the open structure prior to a metal fill material, and excluding effects of any doping material on the metal fill material.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: The invention relates to a method for contactless recording of a track geometry of a track by means of a rail vehicle which is moved along the track on on-track undercarriages (4), wherein profile data of the track extending in transverse direction are compiled by means of a laser scanner. In this, it is provided that, by means of an evaluation device, profile data are evaluated relative to a reference base pre-defined on the rail vehicle in order to derive from this the course of a track central axis and/or a rail. The invention additionally relates to a rail vehicle which comprise an evaluation device configured for carrying out the method. Thus, no further measuring system is required to determine a track position.

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

Abstract: The present technology relates to an image sensor, a manufacturing method and an electronic device capable of preventing a ghost. In the image sensor, a plate-like transparent member larger than a sensor chip in size is affixed to a side of a pixel array unit of the sensor chip having the pixel array unit in which pixels that perform photoelectric conversion are arrayed. The present technology can be applied to a case of capturing an image by receiving light, regardless of whether the light is visible light or not.

Abstract: An online system receives member-created content. The system identifies member interactions with the member-created content. The system then calculates a creator scores for members, and content scores for content. The system identifies members of the online system as creators when the creator scores transgress a threshold, and the system provides to members of the online system follow recommendations for member based on the creator scores for the members.

Abstract: A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.

Abstract: Provided is a semiconductor package including: at least one first substrate including at least one first substrate terminal extended therefrom; at least one second substrate joined to the upper surface of the first substrate using ultrasonic welding; at least one semiconductor chip joined to the upper surface of the second substrate; a package housing covering the at least one semiconductor chip and an area of the second substrate, where ultrasonic welding is performed; and terminals separated from the first substrate, electrically connected to the at least one semiconductor chip through electric signals, and at least one of them is exposed to the outside of the package housing, wherein a thickness of the terminals formed inside the package housing is same as or smaller than a thickness of the first substrate and the second substrate includes at least one embossing groove on the upper surface thereof.

Abstract: Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

Abstract: An approach is provided for a location-aware evaluation of a machine learning model. The approach, for example, involves designating a geographic area for creating an evaluation dataset for the machine learning model. The approach also involves separating a plurality of observation data records into the evaluation dataset and a training dataset based on a comparison of a respective data collection location of each of the plurality of observation data records to the geographic area. The training dataset is then used to train the machine learning model, and the evaluation dataset is used to evaluate the trained machine learning model.

Abstract: A semiconductor module includes a substrate, a first semiconductor device, a second semiconductor device, a first wiring, a second wiring, a first intermediate layer, a second intermediate layer, and a third wiring. The first semiconductor device is provided on the substrate. The first semiconductor device has a first surface facing the substrate and has a second surface on a side opposite to the first surface. The second semiconductor device is adjacent to the first semiconductor device and is provided on the substrate. The second semiconductor device has a first surface facing the substrate and has a second surface on a side opposite to the first surface. The first wiring is provided on the second surface of the first semiconductor device and is coupled to the second surface of the first semiconductor device. The second wiring is provided on the second surface of the second semiconductor device and is coupled to the second surface of the second semiconductor device.

Abstract: An image sensing device is provided. The image sensing device includes a substrate, a plurality of photosensitive elements, a dielectric layer, a reflector, a color filter, and a microlens structure. The substrate has a first pixel and a second pixel adjacent to the first pixel, and the substrate has a front side and a back side opposite the front side. The photosensitive elements are disposed in the substrate. The dielectric layer is disposed on the back side of the substrate. The reflection is disposed on the front side of the substrate and has a parabolic surface. The color filter layer is disposed on the dielectric layer. The microlens structure is disposed on the color filter layer.

Abstract: Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.

Abstract: Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer.

Abstract: A method for rejecting biased data includes receiving a bias training data set based on a probability distribution of bias-sensitive variables of a target population and segmenting the bias training data set into clusters based on at least one respective bias-sensitive variable of the target population, each cluster including a bias cluster weight. The method also includes receiving a training data set for a machine learning model and segmenting the training data set into training clusters. Each training cluster is associated with at least one corresponding bias-sensitive variable of the target population and includes a corresponding training data set weight. The method also includes adjusting each training data set weight to match a respective bias cluster weight to form an adjusted training data set and providing the adjusted training data set to the machine learning model as an unbiased training data set.

Abstract: Techniques are provided for computing problems represented as directed graphical models via quantum processors with topologies and coupling physics which correspond to undirected graphs. These include techniques for generating approximations of Bayesian networks via a quantum processor capable of computing problems based on a Markov network-based representation of such problems. Approximations may be generated by moralization of Bayesian networks to Markov networks, learning of Bayesian networks' probability distributions by Markov networks' probability distributions, or otherwise, and are trained by executing the resulting Markov network on the quantum processor.

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.