Abstract: Techniques to generate a flavor profile using artificial intelligence are disclosed. A flavor classifier classifies flavors for a given set of ingredients of a recipe from a set of possible classes of flavors. The flavor classifier may use different deep learning models to allow for different granularity levels corresponding to each flavor based on desired preciseness with classification of a particular flavor. A respective flavor predictor may or may not be used for each granularity level based on output of a certainty level classifier used for determining a preceding level of granularity.

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

Abstract: According to the present disclosure, a method of manufacturing a semiconductor device includes the steps of (a) preparing a lead frame including a switching element die pad, a control element die pad, and a third-side side rail portion, (b) mounting a switching element and a diode element on the switching element die pad and mounting a control element configured to control the switching element on the control element die pad, (c) sealing the switching element, the diode element, and the control element with a mold resin such that the power side terminal, the control side terminal, and a part of the third-side side rail portion protrude outward, and (d) forming a third-side side rail terminal by cutting the third-side side rail portion, the third-side side rail terminal extending from a part of the third-side side rail portion.

Abstract: The present technology relates to a semiconductor memory device. The semiconductor memory device includes a plurality of channel plugs disposed in a cell region of a semiconductor substrate, a first dummy region and a second dummy region disposed at both end portions of the cell region, and first dummy plugs disposed in the first dummy region and second dummy plugs disposed in the second dummy region. A critical value of the first dummy plugs arranged in the first dummy region is different from a critical value of the second dummy plugs disposed in the second dummy region.

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

Abstract: Provided a semiconductor chip bonding apparatus including a body, a heater disposed on a lower surface of the body, a collet disposed on a lower surface of the heater, and a head disposed on a lower surface of the collet, the head has a rectangular plate shape, a lower surface and side surfaces of the head are exposed, an upper surface of the head is in contact with the lower surface of the collet, an area of the upper surface of the head is smaller than an area of the lower surface of the collet, the head includes a central section including a recess, and an outer surface constituting a part of the side surfaces of the head, and a peripheral section connected to the recess and disposed on each corners of the head, and a thermal conductivity of the peripheral section is different from that of the central section.

Abstract: Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Abstract: This disclosure describes systems and techniques for detecting events, determining a result of each respective event using a first hypothesis source, and calculating a likelihood that a second (and/or additional) hypothesis source would determine the same result of the respective event. The calculated likelihood may then be used to be determine whether to request that the second hypothesis source determine the result of the event, determine an amount of resources of the second hypothesis source to use to make this determination, and/or like.

Abstract: A lift-off method includes a dividing step of dividing a buffer layer and an optical device layer stacked on a front side of a substrate to thereby form separate buffer layers and separate optical device layers, a transfer member bonding step of bonding a transfer member to a front side of the separate optical device layers, a buffer layer breaking step of applying a pulsed laser beam to the separate buffer layers to thereby break the separate buffer layers, and an optical device layer transferring step of transferring the separate optical device layers from the substrate to the transfer member. An energy density of each pulse of the pulsed laser beam is set to 1.0 to 5.0 mJ/mm2.

Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.

Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that allow improved reliability under high current operation.

Abstract: A system and method for multi-agent reinforcement learning in a multi-agent environment that include receiving data associated with the multi-agent environment in which an ego agent and a target agent are traveling and learning a single agent policy that is based on the data associated with the multi-agent environment and that accounts for operation of at least one of: the ego agent and the target agent individually. The system and method also include learning a multi-agent policy that accounts for operation of the ego agent and the target agent with respect to one another within the multi-agent environment. The system and method further include controlling at least one of: the ego agent and the target agent to operate within the multi-agent environment based on the multi-agent policy.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Abstract: A display device and a method of manufacturing a display device are provided. A display device includes: a substrate; a switching element on the substrate; a first insulating layer on the switching element; a first alignment electrode and a second alignment electrode disposed on the first insulating layer so as to face each other; a second insulating layer on the first alignment electrode and the second alignment electrode; a first driving electrode on the second insulating layer and connected to the switching element; a second driving electrode disposed on the second insulating layer so as to face the first driving electrode; and a light emitting element between the first driving electrode and the second driving electrode, and a distance between the first alignment electrode and the second alignment electrode is less than a distance between the first driving electrode and the second driving electrode.

Abstract: A component joining apparatus, which can realize positioning between a component and a substrate with high accuracy by avoiding influence of thermal expansion of the substrate at the time of joining the component to the substrate by heating at a high temperature, includes a component supply head holding a component and a heating stage heating and holding a substrate, in which a heating region where the heating stage contacts the substrate includes a joining region of the substrate in which the component is joined, and the substrate is larger than the heating stage and a peripheral part of the substrate does not contact the heating stage.

Abstract: Methods and systems for predicting well site production are disclosed, including a computer system comprising one or more processor and a non-transitory computer memory storing processor readable instructions that when executed by the one or more processor cause the one or more processor to receive image data of a geographic region around and including a well site; receive well site location data of a location of the well site; analyze well site data to determine well pad location data of a location of a well pad including an area of observation extending beyond and around a well site; determine pixel data of the well pad within the image data for a particular time from the well pad location data; and analyze the pixel data of the well pad for a particular time to determine a volume of flared gas based on the pixel data.

Abstract: The present disclosure provides a zero moment point jitter processing method as well as an apparatus and a robot using the same. The method includes: obtaining left foot force information and right foot force information collected by sensors; calculating a first zero moment point and a second zero moment point of soles of two feet of a robot based on the left foot force information and the right foot force information; calculating a third zero moment point of the robot according to the first zero moment point and the second zero moment point; calculating a jitter amplitude of the third zero moment point within a preset period; and adjusting a position of the third zero moment point in response to the jitter amplitude being not larger than a predetermined jitter amplitude threshold. In this manner, the robot can eliminate zero moment point jitters within a certain amplitude.

Abstract: Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.

Abstract: Technologies for generating a graph containing clusters of feature attribute values for training a machine learning model for content item selection and delivery are provided. The disclosed techniques include, for each entity, of a plurality of entities, a system identifies transitions from one geographic location to another geographic location. A graph is generated based on the transitions associated with each entity. The graph comprises nodes representing geographic locations and edges connecting the nodes. Each of the edges connects two nodes, represents a transition from one geographic location to another geographic location, and each edge represents an edge weight value that is based on frequencies of transitions between geographic locations represented by the two connected nodes. The system generates a plurality of clusters from the nodes based upon the edge weight value of each edge. The system includes the plurality of clusters as features in a machine learning model.