Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract: A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.

Abstract: An optoelectronic semiconductor device may include a first semiconductor layer, a second semiconductor layer, first and second current spreading structures, and an insulating intermediate layer. The second semiconductor layer may be arranged over a substrate. The first semiconductor layer may be arranged between the second semiconductor layer and the substrate. The first current spreading structure may be electrically connected to the first semiconductor layer, and the second current spreading structure electrically may be connected to the second semiconductor layer. The insulating intermediate layer may include a dielectric mirror and may be arranged between the second current spreading structure and the second semiconductor layer. The current spreading structures may overlap one another in a plane perpendicular to a main surface of the substrate. The first current spreading structure may be arranged at a larger distance from the first semiconductor layer than the second current spreading structure.

Abstract: A silicon carbide semiconductor device includes a metal plate having a first main surface and a second main surface, the second main surface being opposite to the first main surface, an insulating film provided on a portion of the first main surface of the metal plate, a first conductive layer provided on the insulating film, and a silicon carbide semiconductor chip. The silicon carbide semiconductor chip includes a first electrode and a second electrode on a first surface and a third electrode on a second surface, the second surface being opposite to the first surface. The first surface of the silicon carbide semiconductor chip faces the first main surface of the metal plate, the first electrode is bonded to the first conductive layer with a first bonding material, and the second electrode is bonded to the first main surface of the metal plate with a second bonding material.

Abstract: A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

Abstract: A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

Abstract: A display device includes a first pixel including a first light emitting area in which first light emitting elements are arranged, a second pixel including a second light emitting area in which second light emitting elements are arranged, a light blocking pattern disposed on the first and second pixels to overlap a peripheral area of the first and second light emitting areas and including a first opening corresponding to the first light emitting area and a second opening corresponding to the second light emitting area, and a color filter including a first color filter pattern disposed in the first opening and a second color filter pattern disposed in the second opening. The second pixel includes a greater number of second light emitting elements than a number of the first light emitting elements. The second opening has an area smaller than an area of the first opening.

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

Abstract: A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.

Abstract: A semiconductor device includes a substrate, a lower electrode provided over the substrate, a capacitive insulating film, and an upper electrode provided over the lower electrode, wherein the lower electrode has an upper portion and a lower portion, and at a boundary between the upper portion and the lower portion, the diameter of the upper portion is smaller than the diameter of the lower portion.

Abstract: A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

Abstract: Aspects of the present disclosure involve systems, methods, devices, and the like for auto-labeling clusters generated by machine learning models. In one embodiment, a system is introduced that can perform a series of operations for determining comprehensive labels for clusters output from machine learning methods used to classify data sets. The auto-labeling system may include generating labels determined using a computation of a frequency count, ratio, and coverage. These computations may use feature-based dictionaries which aid in the determination, storage, and analysis of the relevant features useful in labeling the clusters.

Abstract: Provided is an IGBT device. The IGBT device includes an MOSFET cell array, where each MOSFET cell includes a p-type body region located at the top of an n-type drift region, an n-type emitter region located in the p-type body region, and a gate dielectric layer, a gate electrode and an n-type floating gate which are located above the p-type body region. The gate electrode is located above the gate dielectric layer, the n-type floating gate is located above the gate dielectric layer, and the gate electrode acts on the n-type floating gate through capacitive coupling. The n-type floating gate of at least one MOSFET cell is isolated from the p-type body region through the gate dielectric layer, and the n-type floating gate of at least one MOSFET cell contacts the p-type body region through an opening in the gate dielectric layer to form a p-n junction diode.

Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.

Abstract: A light-emitting device includes: a first light-emitting element portion including: an n-side nitride semiconductor layer, a first light-emitting layer over the n-side nitride semiconductor layer, and a first p-side nitride semiconductor layer over the first light-emitting layer; a second light-emitting element portion including: a second light-emitting layer over the n-side nitride semiconductor layer, and a second p-side nitride semiconductor layer over the second light-emitting layer; an n-side electrode connected to the n-side nitride semiconductor layer; a first p-side electrode disposed over the first p-side nitride semiconductor layer via an upper n-type semiconductor layer; and a second p-side electrode connected to the second p-side nitride semiconductor layer. The first p-side nitride semiconductor layer and the upper n-type semiconductor layer form a tunnel junction.

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Abstract: A stacked-layer body including a gate insulating film and a control gate electrode is formed in a product region and a scribe region. Next, a gate insulating film and a conductive film are so formed that the stacked-layer body is covered. Next, an etching process is so performed to the conductive film that an upper surface of the conductive film is lower than that of an upper surface of the stacked-layer body, thereby forming a measurement pattern in the scribe region. Next, a memory gate electrode is formed by patterning the conductive film in the product region. Next, a silicide layer is formed on an upper surface of the memory gate electrode in the product region in a state where an upper surface of the measurement pattern is covered by an insulating film. Next, a resistance value of the measurement pattern covered by the insulating film is measured.

Abstract: Techniques regarding determining and/or analyzing temperature distributions experienced by quantum computer devices during operation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a region component that can define a plurality of temperature regions from a quantum computing device layout. The computer executable component can also comprise a map component that can generate a map that characterizes a temperature distribution by determining at least one temperature achieved within the plurality of temperature regions during an operation of the quantum computing device layout.

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.