Patents Examined by Robert L. Richardson
  • Patent number: 6072594
    Abstract: An information signal recording apparatus for recording an information signal having a predetermined frequency band onto a recording medium, which comprises signal separating means for receiving said information signal and for separating the received information signal into a first signal having a first frequency band and a second signal having a second frequency band which is higher than said first frequency band and outputting said first and second signals; first recording means for forming a frequency-modulated first signal by frequency-modulating the first signal outputted from said signal separating means and for recording said frequency-modulated first signal onto a first area of said recording medium; and second recording means for forming a frequency-modulated second signal, which is interleaved relatively to said frequency-modulated first signal, by frequency-modulating the second signal outputted from said signal separating means and for recording said frequency-modulated second signal onto a second
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: June 6, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ryo Fujimoto
  • Patent number: 5444847
    Abstract: A data transfer method for transferring a data frame between a plurality of devices including a controller connected to a serial data bus comprising three lines, that is, a clock line, a data line and a control line. When the control line is at a high level, the controller sequentially distributes tokens, and the control line is kept at a low level by a master while the device which has received the token becomes the master and transfers the data frame. When the control line is at the low level, the controller supplies to the clock line a clock required to transfer the data frame.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: August 22, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Iitsuka
  • Patent number: 5412777
    Abstract: A timing generator 12' applies a control signal SC1 consisting of a row address strobe signal RAS1, a column address strobe signal CAS1 and a writing control signal WE1 to a control input C of a DRAM 31 while it also applies a control signal SC2 consisting of a row address strobe signal RAS2, a column address strobe signal CAS2 and a writing control signal WE2 to a control input C of a DRAM 32. The control signals SC1and SC2 are produced in accordance with the least significant bit LSB of an inside address MA and independent of each other. The display data reading operation can be performed on each of memories (DRAMs) independent of each other, and therefore, the total period for the display data reading can be shortened, and accordingly, a saving of time allows an interruption of a longer period of the display data writing operation during the display period, and thus, a time for a display data renewal can be shortened.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: May 2, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kingo Wakimoto
  • Patent number: 5412781
    Abstract: Buffer memory systems are utilized in communication systems for the transmission of data that arise irregularly over time. These data are stored in memory areas and are subsequently transmitted block-by-block via a data line. The capacity limit of those memory areas is often exhausted, even though an adequate amount of free memory space is still present in the buffer memory system. A buffer distribution method, which is based on a combination of a fixed and of a dynamic buffer allocation method, solves this problem.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: May 2, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Guenter Lukas, Friedrich Ramberger, Siegfried Spahl
  • Patent number: 5410650
    Abstract: A message control system for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In the message control system, each processing module (10, 40) includes a central processing unit (11, 41), a memory unit (12, 42) and a connection unit (13, 43). The connection unit (13, 43) includes at least a logical transmitting port (21, 51) for transmitting a message, a logical receiving port (22, 53) for receiving a message, a transmission system connecting unit (23), a reception system connecting unit (24), a transmitting side fault generation monitoring unit (25) and a receiving side fault generation monitoring unit (26).
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: April 25, 1995
    Assignee: Fujitsu Limited
    Inventors: Takatsugu Sasaki, Akira Kabemoto, Hajime Takahashi, Horihide Sugahara
  • Patent number: 5408614
    Abstract: A modem adapter for use with a standard parallel port of a personal computer (PC) for interfacing to the public switched telephone network (PSTN). The modem adapter accepts digital data, eight bits at a time, from a standard PC parallel port and modulates this digital data into an analog format, compatible with the PSTN. Conversely, the modem adapter accepts analog data from the PSTN and converts it into digital data and transfers this data to the parallel port, at least four bits at a time. The modem adapter of the present invention thus neither requires any additional circuit cards in the PC's card slots nor dedication of any of the existing serial ports. Redirector software intercepts software I/O instructions directed toward a serial I/O port and redirects and reformats these instructions to the modem adapter through the parallel port. This redirection permits existing modem control software to be used without modification with the modem adapter of the present invention.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: April 18, 1995
    Assignee: Xircom, Inc.
    Inventors: Timothy J. Thornton, Robert Rosen, Eric K. Henderson
  • Patent number: 5408589
    Abstract: A diagnosis mode start key provided on a switch panel is operated to execute a diagnosis mode processing routine for an external data storage device by a CPU of a laser printer. Then, the CPU determines whether initialization of the external data storage device, connected to the laser printer, has been completed. If the CPU determines that the initialization of the external data storage device has not been completed, a LCD displays a message "execute initialization?" and the CPU waits ready for a next instruction by a user. If a maintenance execution key is operated by the user, the LCD displays a message "initializing" during initialization. At the same time, an initialization execution processing is executed.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: April 18, 1995
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Ichiro Yamamoto
  • Patent number: 5408639
    Abstract: A processing system of the type having a processor which accesses external memory for data and/or instructions which includes an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of the processing system. The control system includes a selectably programmable clock for providing a clock signal of one of at least two speeds for determining the external memory access rate. The control system also includes enable duration control structure coupled to the selectably programmable clock. The enable duration control structure is arranged to enable the external memory for time durations during each memory access which are independent from the external memory access rate. Further, the enable duration control structure includes substructure for changing the duty cycle of external memory enable time duration control signals based upon the selected clock speed.
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: April 18, 1995
    Assignee: Advanced Micro Devices
    Inventors: Dale E. Gulick, James E. Bowles
  • Patent number: 5408611
    Abstract: An auto-switching device for CPU logic which automatically senses the kind of CPU, and sets the timing margin according to the sensed kind of CPU, and at the same time switches the CPU logic so that a system can be operated in accordance with the sensed kind of CPU in an IBM PC-compatible system using CPUs of the i80486SX, i80487SX and i80486DX type produced, for example by Intel Co. The auto-switching device is constituted by a CPU socket capable of mounting CPU chips of the i486DX, i486SX chip and the like types and being mounted for multiple use. A ROM having built-in software for detecting the kind of CPU at the time of initial operation and a decoder providing the address of a storage medium for storing information about the kind of CPU detected by the software.
    Type: Grant
    Filed: May 20, 1992
    Date of Patent: April 18, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Donguk Kim
  • Patent number: 5404449
    Abstract: Interface module supports communication between processor systems. Communication between processor systems should chronologically burden the processor systems as little as possible. To this end, an interface module is utilized that supports the communication between two processor systems in the form of a process-parallel servicing of the two interfaces to the two processor systems.
    Type: Grant
    Filed: August 5, 1992
    Date of Patent: April 4, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Juergen Weber, Werner Nagler, Gerd Boecker
  • Patent number: 5404459
    Abstract: A serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By ANDing the clock output signal with a data output signal of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device.
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: April 4, 1995
    Assignees: Advanced Micro Devices, Sony Corporation
    Inventors: Dale E. Gulick, Alan F. Hendrickson, Munehiro Yoshikawa, Hiroshi Matsubara, Kazushige Tsurumi
  • Patent number: 5396595
    Abstract: A method and system for compressing and decompressing data is provided. In preferred embodiments, a computer system compresses a data buffer comprising a plurality of symbols wherein each symbol has one or more occurrences. The system generates a symbol table containing each symbol and having a corresponding index. For each occurrence of the symbol in the data buffer, the system determines the index for that symbol into the symbol table, and encodes the index into a variable-length portion, a delimiter, and a fixed-length portion. The system then outputs the encoding as the compressed data buffer.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: March 7, 1995
    Assignee: SpaceLabs Medical, Inc.
    Inventor: Benje J. Standley
  • Patent number: 5394525
    Abstract: There is disclosed a device in which detection data regarding whether the write data into a memory to store image data and the read-out data coincide or not is generated every unit data amount and the access to the memory is controlled in accordance with evaluation data obtained by evaluating the detection data in accordance with a degree of influence on an image, thereby enabling the memory to be effectively used. Information indicative of the degree of influence on the image includes the bit position of the pixel data consisting of a plurality of bits, the position of each pixel data on the screen, the density of pixels corresponding to the invalid memory cells in the memory, and the like.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: February 28, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ichiro Kuwana, Koichi Ueda, Hirofumi Nakajima
  • Patent number: 5394473
    Abstract: The invention relates in general to high-quality low bit-rate digital transform coding and decoding of information corresponding to audio signals such as music signals. More particularly, the invention relates to signal analysis/synthesis in coding and decoding. The invention can optimize the trade off in transform coders between time resolution and frequency resolution by adaptively selecting the transform block length for each sampled audio segment, and/or can optimize coding gain by adaptively selecting the transform and/or by adaptively selecting the analysis window or the analysis/synthesis window pair.
    Type: Grant
    Filed: December 11, 1991
    Date of Patent: February 28, 1995
    Assignee: Dolby Laboratories Licensing Corporation
    Inventor: Grant A. Davidson
  • Patent number: 5392404
    Abstract: A method and system for monitoring and controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least first and second input/output devices each having a coprocessor incorporated therein. The system bus electrically interconnects the system devices and system memory. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. In addition, the memory controller may serve as a bus master on behalf of a slave device requesting access to the system bus. The input/output devices have control logic incorporated therein for (i) determining when an alternate input/output device requests control of the bus, (ii) outputting a preemption signal in response to the alternate request, and (iii) relinquishing control of the bus in response to the preemption signal.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: February 21, 1995
    Assignee: International Business Machines Corp.
    Inventor: Stephen P. Thompson
  • Patent number: 5392403
    Abstract: A circuit arrangement is disclosed for data conversion in an asynchronous, bidirectional data transmission between a serial data interface of a personal computer and a serial data interface of an expansion point of a communication equipment, particularly a subscriber terminal equipment. The procedures implemented in the microprocessor module of the circuit arrangement convert data for the selection of a telecommunication subscriber into a pulse sequence corresponding to the communication equipment, and also convert communication procedures between the personal computer and a communication equipment as well as status requests of performance features of the communication equipment.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: February 21, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Kaufmann
  • Patent number: 5392398
    Abstract: In a cooperative processing system, a client sends bundles of padded messages to a server which receives the messages, processes them and deallocates the storage for each message piecemeal. A storage manager of the server handles integer multiples of some minimum granularity (n) of storage units, and allows storage to be deallocated in amounts smaller than the amount originally allocated. The client packages and bundles each message into an amount of storage equal to an integer multiple of the server storage granularity, before sending the bundle to the server via a communications transport. The server places the bundle into a single buffer, with each message occupying a corresponding portion of the buffer. Each message is then unbundled for processing in place by the server process to which it was sent, after which its portion of storage is immediately deallocated.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: February 21, 1995
    Assignee: International Business Machines Corporation
    Inventor: Christopher Meyer
  • Patent number: 5392422
    Abstract: The bus of the present invention advantageously utilizes high-speed, source synchronized data transfers and lower-speed, globally synchronized transfers of arbitration and consistency information. In a first embodiment, a high speed clock signal and slower speed clock enable signal are globally distributed from a central arbiter to agents coupled to the bus. A sending agent utilizes the high speed clock signal for source synchronized data transfers by forwarding the high speed clock signal, along with the data, to one or more receiving agents. Thus, the globally distributed clock signal is used to accomplish source synchronized data transfers. Arbitration requests, by contrast, are processed at the slower clock enable signal rate in a globally synchronous fashion. In addition, by communicating data cycles information from the central arbiter to the receiving agent at the slower clock enable signal rate, the present invention avoids resynchronization and the possibility of metastability.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: February 21, 1995
    Assignees: Sun Microsystems, Inc., Xerox Corporation
    Inventors: Jeffrey H. Hoel, Michel Cekleov, Pradeep S. Sindhu
  • Patent number: 5392402
    Abstract: A Broadband Intelligent Network employs an ATM fast-packet switch to route signaling cells from a calling party to a switch port directly connected to a Service Control Point (SCP). The signaling cells carry a service request that requires the support of a network resource, and, in the specific case described herein, the support of the Line Information Data Base (LIDB) to facilitate the establishment of a switched virtual connection to a called party. The SCP acts on the information in the signaling cells and selects the required resource, i.e., the LIDB, and then sends a query cell(s) to the LIDB through a permanent virtual connection in the ATM switch. The LIDB, in turn, acts on the information in the query cell(s) to assemble a response cell(s) with the requested information. The response cell(s) is sent to the SCP through the permanent virtual connection in the ATM switch, thereby enabling the SCP to complete call processing, establish the requested connection, and generate a billing record.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: February 21, 1995
    Assignee: Bell Communications Research, Inc.
    Inventor: Richard B. Robrock, II
  • Patent number: 5392440
    Abstract: A circuit arrangement for operating a computer, having at least one working register into which and out of which information, under specific addresses, can be read, and a readback device for a feedback occurring in a program step whereby the last-written information is fed back to a processor of the computer. The circuit arrangement includes at least one feedback register to which the working register is assigned. A device is provided for writing the respective information under the same address both to the working register and also to the feedback register for storage therein and for writing new information. A device forwards the information stored in the feedback register to the processor.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: February 21, 1995
    Assignee: Heidelberger Druckmaschinen AG
    Inventor: Peter Marten