Abstract: A simplex sequence controller for transmittal of output data is disclosed and includes a time base generator for generating a timing signal, a memory device having a plurality of addressable sequential storage locations for storing a sequence of data pattern with a plurality of output lines and a plurality of input address lines connected to the storage locations, along with an addressing apparatus connected to the memory device input address lines for directing access to predetermined storage locations at predetermined points in the data sequence, and address reset apparatus providing feedback from a first predetermined one of the output lines of the memory device to the addressing apparatus to direct access to a predetermined initial data sequence for output from the memory.

Abstract: An address management system which is integrally compatible to an plurality of communication services and a plurality of communication application programs, and a communication terminal which utilizes such an address management system are disclosed.

Abstract: The present invention is directed to a buffer swapping scheme to communicate a message from a first device to a second device wherein a pointer to a free buffer is returned to the first device by the second device as a condition for the first device to pass a pointer to a buffer containing a message intended for the second device.

Abstract: A portable interprocess communication facility by which different processes running simultaneously on a network of computer systems can efficiently communicate variable sized data blocks between each other. This involves the elements and techniques necessary to achieve high speed communication, without requiring the processes to be located on the same physical system or to be completely dependant upon the particular design or revision of the operating system in which they run. In addition, the invention simplifies the task of porting a modular software system between different hardware devices and operating systems by allowing communicating processes to be only loosely connected to the operating system.

Abstract: A disk controller which fragments host requests into atomic requests or one cycle operations prior to execution. The disk controller is coupled to a disk array and receives requests from a host CPU. Host requests are fragmented down to atomic operations. This is highly advantageous for error handling because the controller is not required to determine which phase of an operation is being requested, since every operation is single phase. The present invention includes use of fence markers or execution-control markers to "fence" of mark a block of tasks and ensure that the atomic operations are executed in sequence, if necessary. These markers ensure that related sequences of atomic operations are kept together without, for example, possibly disruptive intervening writes.

Abstract: In a system comprising a data processing unit and at least one output device, the data processing unit extracts from output information prepared by an application program media resource information needed in outputting the output information from the output device. The data processing unit reads needed media resource information from media resource storage on the basis of the extracted information, downloads the read media resource information into the output device and then outputs the output information to the output device to initiate an outputting process.

Abstract: Circuitry, and associated methodology in a parallel processing system for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus (60) provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with a global clock (31), state alignment circuit (41, 42, 43) to synchronize the processors with the global clock buffers (140, 240, 340) for storing data received off the bus, and circuitry (130, 230, 330) for selectively enabling the buffer to accept those segments of data having addresses allocated to the given processor. To ensure that processing states are aligned, each state alignment circuit inhibits incrementing of the global clock until each corresponding processor transceives necessary data over the bus.

Abstract: A special type of random access memory referred to as video random access memory (VRAM) is used through to provide multiple access to the memory in a timely manner. The VRAM is characterized by a random access port which enables random accessing to the memory array and a serial port comprising a shift register for outputting a large group of bits of data, such as pixels representative of a scan line of a video image, which are rapidly output by the memory. In the present invention, the VRAM is utilized in a different manner to provide more efficient use of memory without degradation in system performance. The VRAM provides for communications between processors as well as the memory utilized by the coprocessor for storage of code and data. Communications between processors is performed through the serial port; therefore, data is communicated via blocks of data transfers minimizing the frequency of access to the memory array.

Abstract: Disclosed is an image pick-up device which uses a charge transfer type solid state image pick-up device, and further is provided with a shutter so as to form a high quality picture signal in such a manner that the smear is prevented by prohibiting the incidence of the light on the device while the charge is transferred in the device. Further, the device is driven by a clock signal for still photographing in order to obtain a high quality picture information for one frame surely. Further, the photographing parameter is automatically changed over or the monitor is changed over between the motion picture photographing mode and the still photographing mode.

Abstract: A translator suitable for use in a computer system provides an interpreter and a translation table defining a state machine. The interpreter steps through the states of the state machine defined in the translation table to perform translation of input characters or codes into output characters or codes. The interpreter is fixed, and does not affect the translation to be performed. The translation function is defined entirely within the translation table, and selecting a different translation table for use by the interpreter selects a different translation function. All of the required actions are defined in the translation table with no additional external procedures being required.

Abstract: This invention relates to network apparatus for the interconnecting personal computers and workstations, for the purpose of efficiently sharing the use of multimedia type computer applications such as programs and files. Multimedia computer programs are those that display on the user's monitor, text information, computer generated graphical information, and all type of picture image information both moving and still images. Disclosed is apparatus for deploying user input/output components of said personal computers and workstations at a desktop location several kilometers from the physical location of said personal computers. The invention embodied herein uses fiber optics transmission and user controlled optical switching. User control is via the Public Switched Telephone Network. The invention provides three advantages to a user such as an educational institution, software savings, hardware savings, and software security.

Abstract: Optimized indication signals of a completed data frame transfer are generated by a network adapter which reduces host processor interrupt latency. The network adapter comprises network interface logic for transferring the data frame between the network and a buffer memory and host interface logic for transferring the data frame between the buffer memory and the host system. The network adapter further includes threshold logic where a threshold value in an alterable storage location is compared to a data transfer counter in order to generate an early indication signal. The early indication signal may be used to generate an early interrupt signal to a host processor before a transfer of a data frame is completed. The network adapter also posts status information status registers which may be used by the host processor to tune the timing of the generation of the network adapter interrupt signal.

Abstract: In a computer system executing a dynamically configurable operating system, a symbol definition image file builder is provided for building a symbol definition image file real time for utilities and application programs. The symbol definition image file is built upon receipt of an open request for the file and a current system definition image file does not exist. The symbol definition image file is deleted upon receipt of a close request for the file and it is determined that the file is no longer referenced and non-current. The symbol definition image file comprises all current symbol definitions and strings of the operating system. The current symbol definitions and strings are gathered by the symbol definition builder from the symbol and string tables of the root executable segment and the relocatable segments of the operating system that are currently loaded in memory.

Abstract: A computer system eliminates overhead due to overlapping input processing for a keyboard, etc., by two operating systems, where one is a minor operating system operating as a subprocess of the other, which is a main operating system. The system uses an interrupt from a keyboard interface for input processing. A data input from the keyboard is determined as to whether or not it has been assigned to the minor operating system. If it has been assigned to the minor operating system, the key data is written directly to the key data buffer by the driver of the main operating system. The application program executable under the minor operating system can receive key data from a keyboard driver of the minor operating system.

Abstract: An ink sensing system for a vector plotter in which a pen is adapted to be raised and lowered from a drawing media surface along a system axis. An optical detection system is provided which has a focal point on the system axis and below the media surface when the pen is in its lowered position and at the media surface when the pen is in its raised position. The optical detection system includes a source of illumination and a detector system to determine the degree of reflectance from the media surface to indicate the presence or absence of ink on the media surface. In a particular embodiment the optical detection system is moveable and the movement of the optical detection system is coupled to the movement of the pen. Furthermore, the focal point of the optical detection system coincides substantially with the last point of contact of the pen with the media surface when the pen is in the raised position.

Abstract: A network interface controller controls communication between a host system and a network transceiver coupled to a network comprises a memory outside of the host address space in which receive and transmit buffers are managed, host interface logic emulating memory mapped registers in the host address space, for transferring data between the host address space and the buffer memory, and network interface logic coupled with the network transceiver, for transferring data between the buffers in the buffer memory and the network transceiver. The buffer memory includes a transmit descriptor ring buffer, transmit data buffer, transfer descriptor buffer, and receive ring buffer all managed by operations transparent to the host.

Abstract: Determinism is maintained in a synchronous first system although the first system receives behaviorchanging signals from a second system running asynchronously relative to the first system. The second system refrains from sending behavior-changing signals to the first system until the first system stops its clock at a prespecified clock cycle and signals the second system of the event. The second system then downloads the behavior-changing signals into the first system and restarts the first system clock. The first system awakens to discover that the behavior-changing signals have been received during the prespecified clock cycle. This is repeated over multiple runs, and in each run the same behavior-changing signals are transferred at the same prespecified clock cycles of the first system. Deterministic behavior is thereby maintained in the first system.

Abstract: Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached.

Abstract: A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.

Abstract: A method and apparatus for fairly allocating a shared resource among N operating devices of a computer system. The resource allocation is implemented by operating the shared resource to process data for each of the N operating devices in a round robin manner, through a series of time slots. The shared resource processes up to a fixed maximum amount of data during each time slot.