Abstract: A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion.

Abstract: A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transfer to selected ones of the processing nodes as identified by associated request address information, and receives processed data in response, the request address information identifying selected ones of the processing nodes to receive a processing request in parallel. The request distribution network distributes the processing requests to the processing nodes and returns processed data to the control node. The network includes a plurality of request distribution nodes connected in a plurality of levels to form a tree-structure, including an upper root level and a lower leaf level.

Abstract: The functions of two virtual operating systems (e. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: An apparatus for managing communication within a computing system which includes a processing unit and a plurality of peripheral units. The processing unit receives information from a plurality of loci within the computing system and determines an enablement profile in response to such information according to predetermined criteria. The processing unit responds to the enablement profile to selectively enable specified peripheral units. The apparatus comprises a monitoring circuit for monitoring the enablement profile; a logic circuit for logically treating the enablement profile and generating a feedback signal representative of the enablement profile; and a transmission circuit for communicating the feedback signal from the logic circuit to the processing unit. The processing unit responds to the feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until the non-enabled unit is enabled.

Abstract: An I/O request time limit value is set in a request-based, device-based, data-set-based, or workload-based time limit field, for transactions performing I/O operations to I/O devices in a data processing system. A scan routine compares the total time for the I/O request (including waiting time and retry time) against the appropriate time limit(s), and terminates the I/O request if the time limit is exceeded. If an active I/O request is interrupted as a result of an I/O error, retry is prohibited if the total I/O request time (including retry time) exceeds the appropriate time limit, or is within a threshold value of the appropriate time limit.

Abstract: There is disclosed a circuit for controlling the generation of a busy signal and an acknowledge signal properly to allow fast, accurate data communication between communication systems.

Abstract: A method and apparatus for determining whether an alias (or entity name) is available for use in a communication system. A transmitting node or entity transmits a first signal including the alias over the communication system. The alias includes a zone name. If the transmitting node receives a reply signal to the first signal, then the alias is not available for use. Otherwise the alias is available for use. The transmitting node transmits the first signal to a first router connected to a first local network of the communication system. The first router forwards a second signal including the entity name from the first signal to other routers in the network until a second router connected to nodes having the zone name in the entity name is located. Each second router translates the second signal into a third signal which includes the alias, and using a first zone multicast address, multicasts the third signal to a first set of nodes.

Abstract: A communication interface between a port driver and an port adapter of a host computer includes a singly-linked queue resident in a host memory of the computer. The queue includes a header element and a stopper element with message entries linked therebetween. The message entries contain information to be exchanged between the port driver and port adapter. Each message entry includes at least a carrier that contains a forward link pointer to the next entry in the queue and message/response specific control information. The stopper element identifies the end of the queue and is distinguishable from a message entry by a valid indicator, e.g., the state of at least one bit of the forward link pointer. Functionally, the stopper entry allows the port driver and port adapter to concurrently insert and remove message entries of the singly-linked queue in a reliable manner without the use of any external synchronization mechanism.

Abstract: A method and apparatus for automatically resolving I/O address conflicts among hardware adapters coupled to a common bus in a computer system. System I/O software tests each address space of a set of possible automatic conflict resolution (ACR) adapter address spaces for bus conflicts between the ACR adapters and non ACR adapters. For each address space having a conflict, the system I/O software shifts the address spaces of the ACR adapters to a next sequential address space of the set of possible address spaces. Thereafter, the system I/O software reallocates the address space of each ACR adapter, such that the address spaces of the ACR adapters do not overlap, and are not in conflict with the non ACR adapters.

Abstract: The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus bottleneck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.

Abstract: The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e.

Abstract: A peripheral controller is described which is suitable for connecting a selected one of a plurality of peripheral devices to a computer system. The peripheral controller comprises programmable bidirectional line driver/receiver devices which can be operated in an input only mode, an output only mode or a bidirectional mode and which can be set into an appropriate mode by configuration control data sent from the computer system to the peripheral controller. The peripheral controller also includes a re-configurable logic array which can be configured under the control of the configuration control data to implement a particular interface required for the selected peripheral device. This increases the efficiency of use of a peripheral interface.

Abstract: An image processing apparatus for expanding given compressed image data in combination with other compressed image data, provided with a retaining device which retains, at the successive expansions of the compressed data, information relative to the development of a certain area until the data development of an area next to the above-mentioned certain area.

Abstract: A bidirectional wait control system for controlling data movement between a slower-speed host module and a faster-speed slave module by means of a bus interface, comprises: a first wait control signal generating means in the host module, capable of generating a first wait control signal synchronizing with that of the bus interface; a second wait control signal generating means in the slave module, responsive to the first wait control signal, capable of generating a second wait control signal synchronizing with that of the bus interface; and means, upon each module having been presented with the wait control signal from the other module, for terminating data movement between the host module and the slave module.

Abstract: The present invention comprises a plurality of processor modules and shared storage modules connected through a system bus. It improves system performance by limiting the range and shortening the time of exclusive control when a CSI (compare and store interlocked) instruction is executed to rewrite the contents of a shared storage if read data at an accaccaccess address of a shared storage coincide with the data anticipated by a CPU. In the present invention, when the CPU of the processor module rewrites data by addressing any shared storage module in executing a CSI instruction, the CPU has a connection unit connected through a system bus of a shared storage module recognize the CSI instruction, and reads data and compares them with comparison data in the shared storage module. Thus, the range of the exclusive control is limited to the process in the internal bus in the shared storage module.

Abstract: A device for managing a plurality of independent queues in a common non-dedicated memory space uses a set of memory space resource use vectors with one vector per managed queue. A vector defines a list of free memory space locations. Read and write pointer registers store the address of memory locations last written or read and a circuit for evaluating the closest successor of these latter memory locations. The device has the advantage of enabling all memory resources to be used, the same resource being usable by any queue.

Abstract: This video graphics display system includes an apparatus that allows any portion of the complete image to be displayed independently. Focusing on a specific area of an image, or panning, results in a significant change in the relationship between the data stored in the video memory and the arrangement of the pixels on the monitor. This display system recalculates the timing and location of the multiple data transfers necessary to display any portion of the graphics data held in memory. The required data transfers are performed through a handshake between the SMT02 and the BSR03. This handshake allows data transfers to occur during the monitor blanking period and in spite of restrictions imposed by the video memory specifications.

Abstract: A mechanism and method for setting display modes in computer systems associates a unique mode data set and identity (ID) function to each type of display monitor that is supported for attachment to the system. At system installation, mode data sets associated with all monitor types then supported by the system are stored on the system's hard disk in association with each video adapter currently active in the system and with the ID functions of the respective monitor types. Connectors which attach monitors to the system are constructed to provide indications of respective ID functions. Each connector has m ID indicating pins (m>1) which can be sensed by the system and used to form ID functions n bits long (where n is greater than m). Each time the system is powered on after installation, the ID function of the currently installed monitor, and other key data associated with the currently installed video adapter(s), are sensed and stored in a predefined location in system memory accessible to the system BIOS.

Abstract: The interprocess message queue operates in a multiprocessing environment to ensure that interprocess messages sent from an originating task do not overflow the destination task resource pipe. To prevent message overflow, the destination task creates a message queue when a communication session is originated and populates this message queue with n message reserved for the originating task. Each time the originating task wishes to send a message to the destination task, the originating task first retrieves one of the reserved messages from the destination task message queue. Once the message is retrieved from the message queue, the originating task is assured that memory space is available in the resource pipe to send a message. When the destination task receives the message, the destination task reads the message and flags the message as old, thereby allowing another message to be sent, since the originating task can now remove this old message from the message queue to make room for a new message.

Abstract: Several techniques are used to optimize the transmission of signals or events from one bus to the other. In one aspect, the user of a chipset is permitted to choose whether the originating events (i.e. the events in response to which a destination event is to be generated on a destination bus) are to be generated synchronously or asynchronously with the clock signal on the destination bus. Whether synchronous or asynchronous generation is chosen, the chipset may perform a synchronization function in response to an originating bus predictor signal. The number of destination clock cycles to delay before generating the desired destination bus event is responsive to the relative frequencies of the clock signals on the two buses, thereby accommodating a wide variety of such relative frequencies.