Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.

Abstract: There is presented an apparatus and method of locating a reflective anomaly in an optical fiber. An optical generator is positioned at one end of a light path extending to and from a reflective anomaly in an optical fiber, and periodic pulses of light are injected into the fiber. A bend coupler containing directional optical detectors is clamped to the optical fiber in mid-span, between the optical generator and a reflective anomaly, and light energy is tapped. The coupler is capable of detecting and discriminating light travelling in both longitudinal directions. After signal conditioning and digitization, the light pulses are submitted to a logical network to initiate a timer that measures a time interval between the event of an interrogating light pulse, and its reflection, the result being memorized in a buffer. A microprocessor controls the system, and computes distance between the attached bend coupler and the reflective anomaly as a function of the memorized time interval.

Abstract: A package and method for packaging optoelectronic or electronic components is provided in which multiple chip regions are packaged simultaneously prior to sectioning of the wafer into chips. The method and package allows micro-optic and other package elements to be integrated onto wafers on the same face as the optoelectronic or electronic devices without inhibiting the ability to make electrical contact to the devices. The package elements may be integrated to the wafer by material deposition, by spinning, or by physical mounting.

Abstract: A method of forming ROM transistor memory cell including not forming lightly doped regions in the semiconductor substrate for some of the memory cells so as to form one type of memory cell and forming the lightly doped regions in another type of memory cell.

Abstract: An erasable-programmable read only memory (EPROM) allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM includes a semiconductor substrate, a field insulating layer defining a device formation region of the semiconductor substrate, a gate insulating layer and a floating gate formed on the field insulating layer and the field insulating layer. The EPROM further includes a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer so that one of the side walls of the trench insulating layer is self-aligned with the end face of the floating gate. A first interlaminar insulating layer covers the floating gate, and a control gate is located above the first interlaminar insulating layer. A second interlaminar insulating layer is formed over the control gate and a bit line is formed on the second interlaminar insulating layer.

Abstract: This invention is a DRAM array having stacked-capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability.

Abstract: A combination of a semiconductor region essentially consisting of Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1), an insulating film formed on the surface of the semiconductor region and essentially consisting of GaAs.sub.x P.sub.y O.sub.z (w, y, z>0), and a passivation film formed on the insulating film and made of an insulating material different from the insulating film. The laminated insulating film has an extremely low leakage current. An excellent MISFET can be realized by forming a gate electrode on the surface of the laminated insulating film.

Abstract: A compound semiconductor device suitable for an infrared ray detector comprises a substrate composed of indium antimonide (InSb), a first conductive layer deposited on the substrate and composed of tin-indium antimonide represented by the formula Sn.sub.x (InSb).sub.1-x, where 0.05.ltoreq.x.ltoreq.0.3, a second conductive layer that is a semiconductor region (active region) formed on the first conductive layer, and electrode provided on the second conductive layer, and a surface protective film formed on the first conductive layer except for the electrode portions.

Abstract: A method for fabricating a flash-EPROM comprises the steps of forming a first gate insulation film and a second gate insulation film on a semiconductor substrate so as to respectively cover first and second device regions, providing a first conductor layer so as to cover both the first device region and the second device region, patterning the first conductor layer to form a floating gate electrode in correspondence to the first device region, oxidizing a surface of the first conductor layer to form a capacitor insulation film surrounding the floating gate electrode, providing a second conductor layer on the first conductor layer as to bury underneath the floating gate electrode covered by the capacitor insulation film, patterning the second conductor layer on the first device region to form a control gate electrode, exposing the first conductor layer in correspondence to the second device region, and patterning the first conductor layer remaining on the second element region to form a gate electrode of a per

Abstract: A method of detecting the positional relationship between a first object and a second object is disclosed which includes projecting a first light through a convex lens mark of the first object and a concave lens pattern of the second object onto a first plane and projecting a second light through a concave lens mark of the first object and a convex lens pattern of the second object onto the first plane, wherein a first spacing between positions of incidence of the first light and the second light on the first plane increases with displacement of the second object relative to the first object in a predetermined direction.

Abstract: An isolation structure is provided to give improved protection from below ground current injection. A first epitaxial region is provided between a power field effect device and nearby control circuitry. The first epitaxial region is tied to the substrate, and the ties are located between the first epitaxial region and the power field effect device. On the opposite side of the power device, preferably adjacent an edge of the integrated circuit chip, a second epitaxial region is formed. This epitaxial region is connected to the first epitaxial region, preferably by a metal interconnect line. A second set of substrate contacts is located between the power device and the second epitaxial region, and is tied to ground. The second epitaxial region encourages injection of current at a location spaced away from the control circuitry.

Abstract: A flow of liquid containing floating fine particles is formed in a flow path, thereby causing successive movement of the particles. A light beam having intensity distribution from a laser is focused on the liquid flow, whereby the particle is optically trapped at the irradiating position, thus being stopped against the liquid flow or being slowed by a braking force. This phenomenon is utilized in controlling the spacing of the particles in the flow or in separating the particles.

Abstract: An Electrically Erasable PROM (E.sup.2 PROM) according to the present invention includes a semiconductor substrate of a first conductivity type having a field oxide formed on a predetermined region of the main surface thereof; a memory section formed on the semiconductor substrate; and a peripheral circuit section formed in the peripheral of the memory section, wherein the peripheral circuit section has a CMOS structure in which an N-channel MOS transistor and a P-channel MOS transistor are connected to each other in a complementary manner; one of the N-channel MOS transistor and the P-channel MOS transistor is a thin film transistor formed on the field oxide and the other is a MOS transistor formed on the semiconductor substrate; and the memory section includes a plurality of non-volatile transistors formed on the semiconductor substrate.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract: In a semiconductor device having a digital circuit region and an analog circuit region formed on an N type semiconductor substrate, a P type well region is formed on the semiconductor substrate and between the digital circuit region and the analog circuit region. Furthermore, an N type first diffusion layer is formed on the well region. In the semiconductor device, the isolating portion formed between the digital and analog circuit regions not only shuts off an electrical noise between the regions but also absorbs an electrostatic surge input from an external device to a power source terminal, thereby protecting the digital and analog circuit regions from electrostatic breakdown.

Abstract: A terminal pattern is provided for an integrated circuit device, such as a ball grid array package or an integrated circuit flip chip. The terminal pattern is composed of a number of terminals arranged in concentric arrays, each array having a substantially circular shape and being composed of a number of terminals. The terminal pattern is composed of at least two arrays, and more typically three or more arrays. When the integrated circuit device is mounted to its intended substrate, the individual terminals of the terminal pattern each register with and are soldered to a corresponding conductor of a conductor pattern formed on the substrate. A significant advantage is that, due to the terminals of the terminal pattern being arranged in concentric arrays, a smaller maximum width for the terminal pattern is achieved than possible with a conventional rectangular terminal pattern having the same number of terminals.

Abstract: A Fourier-transform (FT) infrared (IR) spectrometer includes a Michelson interferometer without an IR beam compensator. An input IR beam is directed through a substrate and a beamsplitter attached to the substrate for support, with the input IR beam divided by the beamsplitter into a first beam portion incident upon a fixed retroreflector and a second beam portion incident upon a movable retroreflector. The first and second beam portions are then recombined to provide an uncompensated output IR beam with an interference pattern which is directed onto a sample to provide an uncompensated interferogram. The uncompensated interferogram is converted from a time domain to a frequency domain via a Fourier-transform to provide a complex intermediate spectrum, followed by a calculation of a corrected phase angle in terms of wavenumber arising from the substrate's optical thickness. The complex intermediate spectrum is then rotated by a negative of the corrected phase angle.

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.