Patents Examined by Robert P. Limanek
  • Patent number: 5541436
    Abstract: High quality ultrathin gate oxides having nitrogen atoms therein with a profile having a peak at the silicon oxide-silicon interface are formed by oxidizing a surface of a monocrystalline silicon body in an atmosphere of nitrous oxide (N.sub.2 O) at a temperature above 900.degree. C. preferably in the range of 900.degree.-1100.degree. C., and then heating the silicon body and oxidized surface in an atmosphere of anhydrous ammonia to introduce additional nitrogen atoms into the oxide and increase resistance to boron penetration without degrading the oxide by charge trapping. The resulting oxynitride has less degradation under channel hot electron stress and approximately one order of magnitude longer lifetime than that of conventional silicon oxide in MIS applications.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: July 30, 1996
    Assignee: The Regents of the University of Texas System
    Inventors: Dim-Lee Kwong, Giwan Yoon, Jonghan Kim
  • Patent number: 5541424
    Abstract: An electronic component especially a p-channel or n-channel permeable base transistor (PBT) is provided as a plurality of layers, fabricated in a laminated composite, and with at least one laterally structured layer provided for controlling a space charge zone, especially a base of the electronic component.
    Type: Grant
    Filed: July 23, 1994
    Date of Patent: July 30, 1996
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Jurgen Graber
  • Patent number: 5541450
    Abstract: A ball-grid array (BGA) semiconductor package (10,60,90) includes a substrate (31,61,91) attached to a support substrate (32,62 92). The substrate (31,61,91) has an opening (33) extending from an upper surface to a lower surface. An integrated circuit chip (18) is attached to the support substrate (32,62,92) within the opening (33). Bond pads (22) on the integrated circuit chip (18) are electrically connected to ball pads (42,73,106,108) on the lower surface of the substrate (31,61,91). Conductive solder balls (26) are attached to the ball pads (42,73,106,108). The support substrate (32,62,92) provides a low profile and functions as a standoff that limits the collapse of the conductive solder balls (26) when the BGA semiconductor package (10,60,90) is attached to an application board (46).
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: July 30, 1996
    Assignee: Motorola, Inc.
    Inventors: Tim Jones, Denise Ommen, John Baird
  • Patent number: 5541427
    Abstract: A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: July 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Barbara A. Chappell, Bijan Davari, George A. Sai-Halasz, Yuan Taur
  • Patent number: 5541441
    Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed in the antifuse cell opening to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer, and a top electrode disposed over the second barrier metal layer.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: July 30, 1996
    Assignee: Actel Corporation
    Inventors: Yen Yeuochung, Shih-Oh Chen, Leuh Fang, Elaine K. Poon, James B. Kruger
  • Patent number: 5541425
    Abstract: A trench is formed on a main surface of a p+ type monocrystalline silicon substrate. A silicon oxide film is formed extending from the inner surface of trench onto the main surface of p+ type monocrystalline silicon substrate. The thickness of a corner portion positioned on the upper end corner portion of the sidewall of trench in silicon oxide film is larger than the thickness of silicon oxide film positioned on the sidewall of trench. An n type polycrystalline silicon layer extending from the inside of trench onto the main surface of p+ type monocrystalline silicon substrate is formed on silicon oxide film. Thus, a semiconductor device having a trench structure with an improved breakdown voltage for an insulating layer positioned on an upper end corner portion of the sidewall of a trench is obtained.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: July 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hidenori Nishihara
  • Patent number: 5539237
    Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: July 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: James R. Todd, Joe R. Trogolo, Andrew Marshall, Eric G. Soenen
  • Patent number: 5539248
    Abstract: A semiconductor device with an improved insulating and passivating layer including the steps of providing a gallium arsenide substrate with a surface, and crystallographically lattice matching an insulating and passivating layer of indium gallium fluoride on the surface of the gallium arsenide substrate. In one embodiment the semiconductor device is a FET and the layer of indium gallium fluoride covers at least an inter-channel area surrounding the gate.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: July 23, 1996
    Assignee: Motorola
    Inventors: Jonathan K. Abrokwah, Danny L. Thompson, Zhiguo Wang
  • Patent number: 5539234
    Abstract: A semiconductor device includes a semiconductor substrate doped with a first conductivity type. The substrate has a surface, with a parallel array of word lines ion implanted as regions in the surface of said substrate. The N+ word lines are of the opposite conductivity type from the P- substrate. A dielectric layer, formed on the substrate above the word lines, is covered with a polysilicon layer doped with a P- conductivity type. A second dielectric layer covers the polysilicon layer. A parallel array of N+ conductivity regions form doped N+ bit lines in the polysilicon layer. Above the N+ bit lines are formed alternating strips of planarized silicon nitride separated by silicon dioxide strips which are covered by a BPSG layer. An etched code pattern is formed extending through the polysilicon layer in a predetermined region providing an encoded RON.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: July 23, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Gary Hong
  • Patent number: 5539230
    Abstract: A chimney capacitor is formed having two plates, of which each is disposed above and contacts a corresponding electrical contact. The electrical contacts facilitate electrical access to the plates of the chimney capacitor. One of the electrical contacts may comprise part of a general wiring layer that may be used for both electrically accessing the capacitor and for general wiring within the IC chip. Formation of the chimney capacitor proceeds by first forming two electrical contacts on an integrated circuit ("IC") chip. A planar insulating layer is formed thereover, and the capacitor is formed at least partially within the planar insulating layer such that each plate is electrically connected to a corresponding electrical contact.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventor: John E. Cronin
  • Patent number: 5539223
    Abstract: A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: July 23, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sugoh, Hisashi Sugiyama
  • Patent number: 5539232
    Abstract: A plurality of segments of small-sized IGBT devices are arranged concentrically in a plurality of rows in a pellet substrate. Each segment has an independent polysilicon gate electrode layer. A gate electrode terminal lead-out portion is provided at a central portion of the pellet substrate. A metal gate electrode layer electrically connects the polysilicon gate electrode layer of at least one of the segments of a unit, which unit is constituted by at least one of the segments arranged radially from the central portion of the pellet substrate towards a peripheral portion of the pellet substrate, to the gate electrode terminal lead-out portion. The metal gate electrode layer includes a trunk wiring portion extending radially from the gate electrode terminal lead-out portion, and a branch wiring portion extending from the trunk wiring portion in a circumferential direction of the pellet substrate and electrically connected to the polysilicon gate electrode layer of each segment.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: July 23, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nakanishi, Satoshi Yanagisawa
  • Patent number: 5536960
    Abstract: A static random access memory (SRAM) has a plurality of static memory cells each of which has a set of cross coupled inverters having first and second inverters. The first inverter has first and second transistors. The second inverter has primary and secondary transistors. Each of the first and the primary transistors may be, for example, a P-channel transistor. Each of the second and the secondary transistors may be, for example, an N-channel transistor. The static memory cell further has a first diode having a first forward direction and a second diode having a second forward direction. The first forward direction is directed from drains of the primary and secondary transistors to a gate of the first transistor. The second forward direction is directed from drains of the first and the second transistors to a gate of the primary transistor.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: July 16, 1996
    Assignee: NEC Corporation
    Inventor: Fumihiko Hayashi
  • Patent number: 5536955
    Abstract: A device for use in rapidly generating integrated circuit structures is disclosed which provides a plurality of objects and primitives, each primitive having a well of one type of semiconductor conductivity, one FET device of the same conductivity type, one other FET device of an opposite conductivity type, a doped polysilicon conductor connecting together the gates of the FET devices, a positive voltage supply, and a negative or ground voltage supply. This device is particularly defined for rapid transformation into integrated circuit structures that produce integrated circuits having optimized cell structures, minimum overall circuit area, high performance, and reliability.
    Type: Grant
    Filed: June 26, 1995
    Date of Patent: July 16, 1996
    Assignees: Toppan Electronics (USA) Inc., Fast Custom Semiconductors
    Inventor: Akhtar Ali
  • Patent number: 5536973
    Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, a bonding wire is bonded to an electrode pad of a semiconductor element by ball bonding. The bonding wire is cut to have a predetermined length, and compressed and crushed into a bump. By doing so, a wire bump electrode is formed on each electrode pad of the semiconductor element. The wire bump electrodes formed on the electrode pads are then bonded to the respective substrate electrodes on a mounting substrate by melting a low-melting metal. As a result, a flip chip bonding structure wherein the semiconductor element and mounting substrate are bonded to each other by the wire bump electrodes, is obtained.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: July 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiro Yamaji
  • Patent number: 5534729
    Abstract: The present invention provides a modular electronic component (10) wherein a sequence: of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: July 9, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Ernest J. Russell
  • Patent number: 5535006
    Abstract: A method of evaluating integrity of adherence of a conductor bond to a substrate includes: a) impinging a plurality of light sources onto a substrate; b) detecting optical reflective signatures emanating from the substrate from the impinged light; c) determining location of a selected conductor bond on the substrate from the detected reflective signatures; d) determining a target site on the selected conductor bond from the detected reflective signatures; e) optically imparting an elastic wave at the target site through the selected conductor bond and into the substrate; f) optically detecting an elastic wave signature emanating from the substrate resulting from the optically imparting step; and g) determining integrity of adherence of the selected conductor bond to the substrate from the detected elastic wave signature emanating from the substrate. A system is disclosed which is capable of conducting the method.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: July 9, 1996
    Assignee: Lockheed Idaho Technologies Company
    Inventors: Kenneth L. Telschow, Bernard K. Siu
  • Patent number: 5532519
    Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: July 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: Claude L. Bertin, John E. Cronin, David J. Perlman
  • Patent number: 5530281
    Abstract: Lead systems of the subject invention include "coplanar leads" and "aplanar leads", which differ in structure at the inner bond finger. Coplanar leads are generally planar along the lead body and the inner bond finger. Aplanar leads are bent or deformed at the inner bond finger, such that the inner bond finger terminus is not in the plane of the lead body but instead is above or below the plane of the lead body. Deforming select inner bond fingers out of the general plane of the lead system provides a spatial separation for the bonding wires which are attached to the inner bond fingers. This spatial separation acts to minimize wire crossing and shorting during fill processes and results in improved semiconductor package yield.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: June 25, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Richard L. Groover, Matthew W. Preston
  • Patent number: 5530276
    Abstract: A nonvolatile semiconductor memory device comprises: a semiconductor substrate; a pair of spaced electrode films formed on a surface of the semiconductor substrate and having respective side faces opposing each other with a gap formed between them; a pair of diffusion layers formed in the surface of the semiconductor substrate and having respective end portions aligned with the side faces of the electrode films; an insulating film covering the gap and the spaced electrode films; a gate electrode formed on the insulating film to cover the gap and to extend above the pair of electrode films; and wiring layers directly connected to the pair of electrode films, respectively.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: June 25, 1996
    Assignee: Nippon Steel Corporation
    Inventor: Shoichi Iwasa