Abstract: A semiconductor device comprises a silicon via-plug within a fine via-hole in direct contact with an inner wall of the via-hole. A metal silicide layer is formed between an interconnection layer and the silicon plug as well as between the silicon plug and a diffused layer formed in a substrate. Shape defects and excessive stresses formed within a fine via-hole are reduced because the via-hole is filled with the silicon plug substantially without a metallic film or a metal silicide film on a sidewall. The metal silicide film is formed by a heat treatment through silicidation reaction.

Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

Abstract: Structures and methods are presented for forming a field shield for a trench capacitor for a memory cell with a contact through insulator along a sidewall of the trench to a desired region of the semiconducting substrate. The desired region is typically held at a substantially fixed potential; in any case it does not include a node diffusion.

Abstract: A semiconductor substrate includes a P-type silicon substrate and an N-type epitaxial silicon layer formed on the substrate. The N-type epitaxial silicon layer is isolatedly separated into first and second N-type island regions by means of a P-type silicon region which extends from the major surface of the epitaxial silicon layer to the substrate. A power element is formed in the first N-type region. The current path of the power element extends in the first N-type island region and in the substrate, i.e., reaches a deep portion of the substrate from the major surface. The logic element is formed in the second N-type island region. The current path of the element extends only in the second N-type island region, i.e., reaches a shallow portion of the substrate from the major surface. A carrier-recombination-center layer is formed in a deep portion of the substrate, and overlaps the current path of the power element.

Abstract: A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Abstract: This invention includes semiconductor devices including the heat sink with a slitted metal strip, such as copper, which is coiled or folded to produce an array of flexible flat fingers for mechanical, thermal and electrical contact with the silicon die, such as a power transistor. The use of a slitted metal strip instead of a bundle of wires makes fabrication of the flexible mount simpler and more economical. The flexible flat fingers are able to accommodate hot spots on the semiconductor device and change in thermal gradients as the device is operated.

Abstract: Silicon wafers containing conductive feedthroughs of an hourglass shape located around their peripheries that can be incorporated into multichip modules that includes silicon wafer spacers having radial grooves for receiving cooling fluid.

Abstract: The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalks thereof. Such a trench can then be utilized to totem a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.

Abstract: Memory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36) are implanted in the semiconductor substrate. Drain regions (38) are also implanted in the column structures (12a, 14a).

Abstract: A bump structure has a bump constituted by a metal projection which is formed on an electrode of a substrate, and a solder which covers the metal projection but does not touch the electrode. The metal projection is substantially spherical and has a projected portion at a center portion on an upper surface thereof. The metal projection is made of a metal having properties of solder diffusion prevention and adhesion to solder. The bump structure may have two bumps, the first bump being substantially the same as the bump described above and the second being such that its diameter is smaller than an outer diameter of the first bump and it covers the projected portion on the first bump. This bump structure can be formed using a simple process, and can be applied to flip-chip mounting in semiconductor devices with high reliability and yield.

Abstract: There is provided a base for an electronic package. The base includes a peripheral portion for a polymer adhesive and a central portion for one or more semiconductor devices. A lead support is adjacent the substrate and located between the peripheral portion and the central portion. When a polymer adhesive bonds a leadframe to the package base, the lead support prevents deflection of the inner lead tips.

Abstract: A power semiconductor component includes a semiconductor body having anode and cathode sides and a given thermal coefficient of expansion. Contact electrodes are each disposed on a respective one of the anode and cathode sides and are made of a metal having a thermal coefficient of expansion differing from the given thermal coefficient of expansion. At least two contact surfaces are disposed one above the other under pressure, between the semiconductor body and the contact electrodes. At least one of the contact surfaces has a layer formed of an amorphous carbon-metal compound.

Abstract: A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.

Abstract: A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Abstract: A vertical type semiconductor device is provided with an improved construction which greatly decreases the on-resistance without impairing the breakdown voltage thereof. In the fundamental DMOS cells that control a current to constitute the vertical semiconductor device, through-hole cells are arranged along the sides of a cell having a channel. The through-hole cell includes a through-hole extending from the surface of an n.sup.- -type drift region toward an n.sup.+ -type drain region, and also includes an n.sup.+ -type through-hole region that is formed by diffusing impurities from the inner wall of the through-hole which is continuous with the n.sup.+ -type drain region. A breakdown voltage of the element is maintained by the n.sup.- -type drift region between a p-type well region and the n.sup.+ -type through-hole region or the n.sup.+ -type drain region.

Abstract: A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact.

Abstract: A solid state image sensor device having an effective light detecting element and a peripheral circuit includes a light-shielding film for shielding a periphery of the effective light detecting element, a first wiring film made of the same material as that of the light-shielding film and formed in the same process as that for the light-shielding film, and a second wiring film of aluminum for the peripheral circuit. The first wiring film and the second wiring film form a two layer wiring structure of the peripheral circuit and are electrically interconnected through contact holes in an interlayer insulating film. With this arrangement, it is possible to lower the wiring resistance for the peripheral circuit and also to cause a signal transfer clock pulse of high-frequency to propagate without its waveform becoming dull.

Abstract: An electronic system circuit package is disclosed herein. The package utilizes a lead frame having an electrically conductive component support segment incorporating provisions for mounting a plurality of electronic components directly on the support segment in accordance with a predetermined circuit design. The circuit package is then encapsulated in a dielectric medium. In a preferred embodiment, at least some of the electronic components are mounted directly to electrically isolated subsegments of the component support segment and electrically interconnected through their respective subsegments to other components.

Abstract: A MOSFET having a nonuniform doping channel and a method for fabricating the same.The MOS transistor having a nonuniform doping channel is comprised of: a gate oxide film formed on a semiconductor substrate provided with a trench; a gate electrode of some size formed on the gate oxide film atop the trench and its surroundings, the gate electrode having a portion longer than any other portion and thus, being asymmetrical with regard to the axis passing the center of the trench; a source region formed in a predetermined portion of the semiconductor substrate neighboring a short portion of the gate electrode; a high density channel region formed by doping impurities having the same type with the semiconductor substrate in a predetermined portion of the semiconductor substrate below a longer portion of the gate electrode; and a drain region formed in a predetermined portion of the semiconductor substrate neighboring the high density channel region.

Abstract: A electrically erasable and programmable memory comprising: a semiconductor substrate; a source region and a drain region formed spaced apart from each other by a definite distance on a main surface of said semiconductor substrate; a channel region provided between the source region and the drain region; a gate insulating film provided on the channel region; a floating gate electrode provided on the gate insulating film; and a control gate electrode provided with an interlayer insulating film sandwiched therebetween so that the control gate electrode at least partially laminates the floating gate electrode; the channel region and the main surface having an inclined portion and the source region being provided relatively above or below the drain region.