Patents Examined by Roberts P Culbert
  • Patent number: 11996296
    Abstract: A substrate processing method includes: (a) carrying a substrate having a first film with a recess, and a mask into a first chamber; (b) adjusting the substrate temperature to 200° C. or higher; (c-1) supplying silicon-containing reactive species into the first chamber, thereby adsorbing the species onto the side wall of the recess; and (c-2) supplying nitrogen-containing reactive species into the first chamber, thereby forming a second film on the side wall of the recess; (d) carrying the substrate into a second chamber; and (e) adjusting the substrate temperature to 100° C. or lower; and (f) etching the bottom of the recess. Further, (a) to (f) are repeated in this order until an aspect ratio of a depth dimension from the opening of the mask to the bottom of the recess becomes 50 or more.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kae Kumagai, Ryutaro Suda, Maju Tomura, Kenji Ouchi, Hiroki Murakami, Munehito Kagaya, Shuichiro Sakai
  • Patent number: 11992914
    Abstract: An object of the present invention is to provide a polishing composition which can make the removal rate of a metal material and the removal rate of a resin material the same or close to each other in a chemical mechanical polishing process, which can accordingly avoid or suppress the occurrence of a step difference. The polishing composition contains: abrasive grains containing silica, with at least a part of hydrogen atoms constituting a silanol group located on a surface of the silica being substituted with a cation of at least one metal atom M selected from the group consisting of aluminum, chromium, titanium, zirconium, iron, zinc, tin, scandium, and gallium; and a dispersing medium. The pH of the polishing composition is more than 2 and 7 or less.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 28, 2024
    Assignee: FUJIMI INCORPORATED
    Inventor: I-Chun Chang
  • Patent number: 11986921
    Abstract: A chemical mechanical polishing method is provided. A chemical mechanical polishing method comprising providing a polishing pad, supplying a first purging compound having a first temperature onto the polishing pad, supplying a first slurry having a third temperature onto the polishing pad supplied with the first purging compound, supplying a second purging compound having a second temperature lower than the first temperature onto the polishing pad, and supplying a second slurry having a fourth temperature lower than the third temperature onto the polishing pad supplied with the second purging compound.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 21, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung-Ki Hong, Yong Hee Lee, Byoung Ho Kwon, Kun Tack Lee
  • Patent number: 11978639
    Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: May 7, 2024
    Assignee: Tessera LLC
    Inventors: Fee Li Lie, Dongbing Shao, Robert C. Wong, Yongan Xu
  • Patent number: 11972949
    Abstract: A device for manufacturing a SiC substrate, in which the occurrence of a work-affected layer is reduced, or from which a work-affected layer is removed, comprises: a main container which can accommodate a SiC substrate and which generates, by heating, a vapor pressure of a vapor-phase species including elemental Si and a vapor-phase species including elemental C in an internal space; and a heating furnace for accommodating the main container, generating a vapor pressure of the vapor-phase species including elemental Si in the internal space, and heating so that a temperature gradient is formed; the main container having an etching space formed by causing a portion of the main container disposed on the low-temperature side of the temperature gradient and the SiC substrate to face each other in a state in which the SiC substrate is disposed on the high-temperature side of the temperature gradient.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: April 30, 2024
    Assignees: KWANSEI GAKUIN EDUCATIONAL FOUNDATION, TOYOTA TSUSHO CORPORATION
    Inventors: Tadaaki Kaneko, Natsuki Yoshida, Kazufumi Aoki
  • Patent number: 11960051
    Abstract: Various embodiments may provide a method of fabricating a meta-lens structure. The method may include forming a first dielectric layer in contact with a silicon wafer. The method may also include forming a second dielectric layer in contact with the first dielectric layer. A refractive index of the second dielectric layer may be different from a refractive index of the first dielectric layer. The method may further include, in patterning the second dielectric layer. The method may additionally include removing at least a portion of the silicon wafer to expose the first dielectric layer.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: April 16, 2024
    Assignee: Agency for Science, Technology and Research
    Inventors: Shiyang Zhu, Chih-Kuo Tseng, Ting Hu, Zhengji Xu, Yuan Dong, Alex Yuandong Gu
  • Patent number: 11955337
    Abstract: A substrate processing method includes: providing a substrate including a mask; forming a film on the mask; forming a reaction layer on a surface layer of the film; and removing the reaction layer by applying energy to the reaction layer.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: April 9, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Takayuki Katsunuma, Shinya Ishikawa, Yoshihide Kihara, Masanobu Honda
  • Patent number: 11948805
    Abstract: An etching method for selectively etching a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 2, 2024
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Xin Wu, Chun Wang, Bo Zheng, Zhenguo Ma
  • Patent number: 11926764
    Abstract: A polishing liquid containing: abrasive grains; a first nitrogen-containing compound; a second nitrogen-containing compound; and water, in which the first nitrogen-containing compound contains at least one selected from the group consisting of (I) a compound having an aromatic ring containing one nitrogen atom in the ring and a hydroxyl group, (II) a compound having an aromatic ring containing one nitrogen atom in the ring and a functional group containing a nitrogen atom, (III) a compound having a 6-membered ring containing two nitrogen atoms in the ring, (IV) a compound having a benzene ring and a ring containing a nitrogen atom in the ring, and (V) a compound having a benzene ring to which two or more functional groups containing a nitrogen atom are bonded, and an HLB value of the second nitrogen-containing compound is 7 or more.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: March 12, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Masayuki Hanano, Hisato Takahashi, Toshio Takizawa
  • Patent number: 11914300
    Abstract: The present invention provides a manufacturing method of a semiconductor chip, in which the manufacturing yield is excellent, and a kit. According to the present invention, a manufacturing method of a semiconductor chip includes Process 1 of forming an insulating layer on a base material, Process 2 of forming a patterned resist film on the insulating layer, Process 3 of forming the insulating layer having an opening portion by etching the insulating layer with the patterned resist film as a mask, Process 4 of removing the patterned resist film, Process 5 of filling the opening portion of the insulating layer with metal, and Process 6 of performing chemical-mechanical polishing on the insulating layer filled with metal.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 27, 2024
    Assignee: FUJIFILM Corporation
    Inventor: Tetsuya Kamimura
  • Patent number: 11915941
    Abstract: The present disclosure provides various embodiments of an improved wet atomic layer etching (ALE) process. More specifically, the present disclosure provides various embodiments of methods that improve a wet ALE process by providing a dynamic ALE cycle timing schedule that balances throughput and etch rate with post-etch surface roughness. As described in more detail below, the methods disclosed herein may adjust the purge timing between ALE cycles and/or between individual surface modification and selective dissolution steps to provide a desired throughput, etch rate and/or post-etch surface roughness in a wet ALE process.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Jacques Faguet, Tetsuya Sakazaki, Paul Abel
  • Patent number: 11901193
    Abstract: A method for fabricating a device having a cavity, includes: obtaining a device wafer including a first substrate and a device structure formed on the first substrate, depositing a first dielectric layer on the device wafer, etching the first dielectric layer to expose at least a part of the device structure and a part of the first substrate, depositing, after the etching, a second dielectric layer on the device wafer and the first dielectric layer, performing a surface treatment on a surface of the second dielectric layer, obtaining a second substrate, and bonding the second substrate with the second dielectric layer on the device wafer, thereby forming the cavity between the second substrate and the device wafer.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: February 13, 2024
    Assignee: Shenzhen Newsonic Technologies Co., Ltd.
    Inventor: Guojun Weng
  • Patent number: 11894239
    Abstract: There is provide a technique that includes: etching a base on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming a layer on a surface of the base by supplying a modifying agent to the base; and (b) causing a reaction between a halogen-containing radical and the base by supplying a halogen-containing gas to the layer such that the layer reacts with the halogen-containing gas to generate the halogen-containing radical.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: February 6, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Motomu Degai, Kimihiko Nakatani, Takashi Nakagawa, Takayuki Waseda, Yoshitomo Hashimoto
  • Patent number: 11887814
    Abstract: Provided is a plasma processing method capable of improving an etching selectivity of a material to be etched with respect to a mask material and reducing a roughness of a side wall of a mask pattern. The plasma processing method of selectively depositing a deposition film on the mask material with respect to the material to be etched includes controlling an etching parameter so that an incubation time of the mask material is shorter than an incubation time of the material to be etched.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 30, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Mamoru Yakushiji, Kenichi Kuwahara, Masaaki Taniyama
  • Patent number: 11884844
    Abstract: A polishing composition used in wafer polishing process for eliminating protrusion around laser mark, thereby achieving a flat polished surface, as well as a wafer polishing method using the polishing composition. A post-polishing composition for elimination of a laser mark remaining after polishing of silicon wafer with a primary polishing composition containing silica particles, water, and a basic compound, the post-polishing composition including silica particles, water, a tetraalkylammonium ion, and a water-soluble polymer, wherein the mass ratio of the tetraalkylammonium ion to SiO2 of the silica particles is 0.200 to 1.000:1; the mass ratio of SiO2 dissolved in the polishing composition to SiO2 of the silica particles is 0.100 to 1.500:1; and the mass ratio of the water-soluble polymer to SiO2 of the silica particles is 0.005 to 0.05:1. The silica particles have an average primary particle diameter of 1 nm to 100 nm.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: January 30, 2024
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Hibiki Ishijima, Eiichiro Ishimizu
  • Patent number: 11881403
    Abstract: A substrate processing method includes an operation for holding a substrate in a horizontal position, the substrate including an amorphous silicon layer having a surface on which an altered layer derived from dry etching is formed, an operation for irradiating the altered layer with ultraviolet rays to reform the altered layer into a reformed layer, and an operation for supplying a chemical solution to the amorphous silicon layer having the reformed layer on the surface to perform wet etching on the amorphous silicon layer. This improves the efficiency of the wet etching on the amorphous silicon layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 23, 2024
    Inventors: Ayumi Higuchi, Yuya Akanishi
  • Patent number: 11875978
    Abstract: A plasma processing apparatus 1 that performs, on a wafer 16 in which a multilayer film in which an insulating film and a film to be processed containing a metal are alternately laminated is formed on a substrate, plasma etching of the film to be processed, includes: a processing chamber 10 which is disposed inside a vacuum container; a sample stage 14 which is disposed inside the processing chamber and on which the wafer is placed; a detection unit 28 which detects reflected light obtained by the wafer reflecting light emitted to the wafer; a control unit 40 which controls plasma processing on the wafer; and an end point determination unit 30 which determines an etching end point of the film to be processed based on a change in an amplitude of vibration in a wavelength direction of a light spectrum of the reflected light, and the control unit receives determination of the end point made by the end point determination unit and stops the plasma processing on the wafer.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 16, 2024
    Assignee: Hitachi High-Tech Corporation
    Inventors: Tsubasa Okamoto, Tatehito Usui, Miyako Matsui, Shigeru Nakamoto, Naohiro Kawamoto, Atsushi Sekiguchi
  • Patent number: 11857343
    Abstract: Methods are provided for the fabrication of microneedles. Microneedles fabricated according to the herein described methods will generally be constructed of multiple lengths of wire winded together, brazed and further manipulated to include a reversible engagement feature. The subject microneedles may find use in a variety of applications and, among other purposes, the reversible engagement feature of such a microneedle may by employed in implanting an implantable device into a biological tissue. Also provided are methods of inserting an implantable device into a biological tissue having an outer membrane. The subject methods may include ablating a section of the outer membrane and inserting the implantable device through the ablated section of outer membrane, including e.g., where the implantable device is inserted using a microneedle including e.g., those microneedles for which methods of fabrication are provided herein.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 2, 2024
    Assignee: The Regents of the University of California
    Inventors: Timothy L. Hanson, Philip N. Sabes
  • Patent number: 11851586
    Abstract: A composition suitable for chemical mechanical polishing a substrate can comprise abrasive particles, a multi-valent metal borate, at least one oxidizer and a solvent. The composition can polish a substrate with a high material removal rate and a very smooth surface finish.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: December 26, 2023
    Assignee: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Lin Fu, Jason A. Sherlock, Long Huy Bui, Douglas E. Ward
  • Patent number: 11851585
    Abstract: A polishing composition includes an abrasive; a pH adjuster; a barrier film removal rate enhancer; a low-k removal rate inhibitor; an azole-containing corrosion inhibitor; and a hard mask removal rate enhancer. A method of polishing a substrate includes the steps of: applying the polishing composition described herein to a surface of a substrate, wherein the surface comprises ruthenium or a hard mask material; and bringing a pad into contact with the surface of the substrate and moving the pad in relation to the substrate.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: December 26, 2023
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Ting-Kai Huang, Tawei Lin, Bin Hu, Liqing Wen, Yannan Liang