Abstract: In one exemplary embodiment, described herein is an ALE process for etching an oxide. In one embodiment, the oxide is silicon oxide. The ALE modification step includes the use of a carbon tetrafluoride (CF4) based plasma. This modification step preferentially removes oxygen from the surface of the silicon oxide, providing a silicon rich surface. The ALE removal step includes the use of a hydrogen (H2) based plasma. This removal step removes the silicon enriched monolayer formed in the modification step. The silicon oxide etch ALE process utilizing CF4 and H2 steps may be utilized in a wide range of substrate process steps. For example, the ALE process may be utilized for, but is not limited to, self-aligned contact etch steps, silicon fin reveal steps, oxide mandrel pull steps, oxide spacer trim, and oxide liner etch.

Abstract: A substrate processing method is described for etching silicon carbide films for resist underlayer applications. The method includes providing a substrate containing a silicon carbide film thereon, and a photoresist layer defining a pattern over the silicon carbide film, plasma-exciting an etching gas containing a fluorocarbon-containing gas and an oxygen-containing gas, and exposing the substrate to the plasma-excited etching gas to transfer the pattern to the silicon carbide film, where at least a portion of a thickness of the photoresist layer survives the exposing. For example, the photoresist layer includes an EUV resist layer and the etching gas includes C4F8 gas, O2 gas, and Ar gas. In another example, the exposing includes exposing the substrate to a) a plasma-excited etching gas containing C4F8 gas, O2 gas, and Ar gas, and b) exposing the substrate to a plasma-excited Ar gas, where steps a) and b) are sequentially performed at least once.

Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate includes applying at least one of low frequency RF power or DC power to an upper electrode formed from a high secondary electron emission coefficient material disposed adjacent to a process volume; generating a plasma comprising ions in the process volume; bombarding the upper electrode with the ions to cause the upper electrode to emit electrons and form an electron beam; and applying a bias power comprising at least one of low frequency RF power or high frequency RF power to a lower electrode disposed in the process volume to accelerate electrons of the electron beam toward the lower electrode.

Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

Abstract: An etching method includes: (a) providing a substrate that contains silicon, on a support; (b) etching the substrate with plasma generated from a first gas that includes a fluorine-containing gas, to form an etching shape having a bottom; (c) generating plasma from a second gas that includes a hydrogen fluoride (HF) gas, to selectively form a condensed or solidified layer of HF at the bottom of the etching shape; and (d) etching the bottom with the plasma generated from the second gas, by supplying a bias power to the support. During (c) and (d), a temperature of the substrate is maintained to be 0° C. or lower.

Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate and define an etch stop layer.

Abstract: A chemical mechanical polishing composition for polishing a ruthenium containing substrate comprises, consists of, or consists essentially of a water based liquid carrier; titanium oxide particles dispersed in the liquid carrier, the titanium oxide particles including rutile and anatase such that an x-ray diffraction pattern of the titanium oxide particles has a ratio X:Y greater than about 0.05, wherein X represents an intensity of a peak in the x-ray diffraction pattern having a d-spacing of about 3.24 ? and Y represents an intensity of a peak in the x-ray diffraction pattern having a d-spacing of about 3.51 ?; and a pH in a range from about 7 to about 10. Optional embodiments further include a pH buffer having a pKa in a range from about 6 to about 9.

Abstract: A method of etching silicon oxide on a surface of a substrate is provided. The method comprises alternately repeating heating the substrate to a heating temperature of 60° C. or higher, supplying hydrogen fluoride gas and ammonia gas onto the substrate to react with the silicon oxide, and modifying the silicon oxide to obtain a reaction product, and removing at least a portion of the reaction product from the substrate while stopping the supply of the above gases and continuing to heat the substrate at the heating temperature; and when a process gas that is at least one of the hydrogen fluoride gas and the ammonia gas is supplied, while continuing to supply the process gas from an upstream side of a flow path, closing a valve disposed in the flow path to pressurize the process gas in the flow path, and then opening the valve.

Abstract: Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.

Abstract: A method for forming a semiconductor device includes depositing a metal resist layer over a layer to be patterned that is formed over a substrate; patterning the metal resist layer using a lithography process to form a patterned metal resist layer and expose portions of the layer to be patterned; selectively depositing a silicon containing layer over the patterned resist layer by exposing the substrate to a gas mixture comprising a silicon precursor, the silicon containing layer being preferentially deposited over a top surface of the metal resist layer; and performing a surface cleaning process by exposing the layer to be patterned and the patterned metal resist layer covered with the silicon containing layer to a plasma process with an etch chemistry comprising a halogen or hydrogen.

Abstract: Disclosed is an atomic-scale processing method by combining extreme ultraviolet light and plasma. The method includes synergistically applying extreme ultraviolet (EUV) light and plasma to treat a surface of a material, enabling atomic-scale processing of the surface of the material.

Abstract: A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below ?20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

Abstract: There is provided a technique that includes: etching a portion of a first film formed on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: supplying an etching gas into a process chamber while raising an internal pressure of the process chamber in a state in which the substrate having the first film formed on the surface of the substrate is accommodated in the process chamber; and lowering the internal pressure of the process chamber by exhausting an interior of the process chamber in a state in which supply of the etching gas into the process chamber is stopped.

Abstract: A method for fabricating an external element or a timepiece dial from non-conductive material, by performing or repeating a basic cycle of making a base from a non-conductive, or ceramic, or glass. or sapphire substrate; dry coating the base with a first sacrificial protective metal layer; etching a decoration with an ultrashort pulse laser to a depth at least equal to the local thickness of the first layer; dry coating the decoration and the remaining part of the first layer with a second metal and/or coloured decorative treatment layer; chemically removing each first layer; and before or after chemical removal of each first layer, mechanically levelling on the upper level of the base the compound thus formed.

Abstract: A slurry containing abrasive grains and a liquid medium, the abrasive grains including first particles and second particles being in contact with the first particles, the first particles containing ceria, the first particles having a negative zeta potential, the second particles containing a hydroxide of a tetravalent metal element, and the second particles having a positive zeta potential.

Abstract: In certain embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes patterning the copper layer, using the patterned layer as an etch mask, by performing a cyclic etch process to form a recess in the copper layer. The cyclic etch process includes forming, in a first etch step, a passivation layer on an exposed surface of the copper layer by exposing the exposed surface of the copper layer to a chlorine gas. The passivation layer replaces at least a portion of a surface layer of the copper layer. The cyclic etch process includes subsequently etching, in a second etch step, the passivation layer using a first plasma that includes a noble gas. Each cycle of the cyclic etch process extends the recess in the copper layer.

Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.